Specifications

Data and Direction Control Registers
5-12
Figure 5–7. Port C Data and Direction Control Register (PCDATDIR)
15 14 13 12 11 10 9 8
C7DIR
C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IOPC7
IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–8 CnDIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bits 7–0 IOPCn
If CnDIR = 0, then:
0 Corresponding I/O pin is read as a
low .
1 Corresponding I/O pin is read as a high .
If CnDIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .
Table 5–7. PCDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)
I/O Port Data Bit Pin Name
IOPC0 W/R/IOPC0
†
IOPC1 BIO/IOPC1
†
IOPC2 SPISIMO/IOPC2
IOPC3 SPISOMI/IOPC3
IOPC4 SPICLK/IOPC4
IOPC5 SPISTE
/IOPC5
†
IOPC6 CANTX/IOPC6
IOPC7
CANRX/IOPC7
†
These pins are not available in ’2402 devices.