Specifications

Data and Direction Control Registers
5-11 Digital Input/Output (I/O)
Figure 5–6. Port B Data and Direction Control Register (PBDATDIR)
15 14 13 12 11 10 9 8
B7DIR
B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IOPB7
IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–8 BnDIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bits 7–0 IOPBn
If BnDIR = 0, then:
0 Corresponding I/O pin is read as a
low .
1 Corresponding I/O pin is read as a high .
If BnDIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .
Table 5–6. PBDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)
I/O Port Data Bit Pin Name
IOPB0 CMP3/IOPB0
IOPB1 CMP4/IOPB1
IOPB2 CMP5/IOPB2
IOPB3 CMP6/IOPB3
IOPB4 T1CMP/IOPB4
IOPB5 T2CMP/IOPB5
IOPB6 TDIR/IOPB6
†
IOPB7 TCLKIN/IOPB7
†
There is no IOPB6 pin in ’2402 devices.