Specifications

Data and Direction Control Registers
5-9 Digital Input/Output (I/O)
5.4 Data and Direction Control Registers
There are six data and direction control registers. Refer to Table 5–1, ’240x
Digital I/O Port Control Registers Implementation , on page 5-3 for the ad-
dress locations of each register.
Figure 5–5. Port A Data and Direction Control Register (PADATDIR)
15 14 13 12 11 10 9 8
A7DIR
A6DIR A5DIR A4DIR A3DIR A2DIR A1DIR A0DIR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IOPA7
IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–8 AnDIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bits 7–0 IOPAn
If AnDIR = 0, then:
0 Corresponding I/O pin is read as a low .
1 Corresponding I/O pin is read as a high .
If AnDIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .