Specifications

I/O MUX Control Registers

5-8

5.3.3 I/O Mux Output Control Register C

Figure 5–4. I/O Mux Control Register C (MCRC) — Address 7094h

15 14 13 12 11 10 9 8

Reserved Reserved MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

76543210

MCRC.7

MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1

Note: R = Read access, W = Write access, -0 = value after reset

Table 5–4. I/O Mux Control Register C (MCRC)

Pin Function Selected

Bit # Name.bit # (MCC.n = 1)

(Primary)

(MCC.n = 0)

(Secondary)

0 MCRC.0 CLKOUT IOPE0

1 MCRC.1 PWM7 IOPE1

2 MCRC.2 PWM8 IOPE2

3 MCRC.3 PWM9 IOPE3

4 MCRC.4 PWM10 IOPE4

5 MCRC.5 PWM11 IOPE5

6 MCRC.6 PWM12 IOPE6

7 MCRC.7 CAP4/QEP3 IOPE7

MCRC.8 CAP5/QEP4 IOPF0

9 MCRC.9 CAP6 IOPF1

10 MCRC.10 T3PWM/T3CMP IOPF2

11 MCRC.11 T4PWM/T4CMP IOPF3

12 MCRC.12 TDIRB IOPF4

13 MCRC.13 TCLKINB IOPF5

14 MCRC.14 Reserved Reserved

15 MCRC.15 Reserved Reserved

Note: Due to the absence of the EVB, bits 1 through 13 must be treated as reserved in the

’2402.