Specifications

I/O MUX Control Registers

5-7

Digital Input/Output (I/O)

Table 5–3. I/O Mux Control Register B (MCRB)

Pin Function Selected

Bit # Name.bit # (MCB.n = 1)

(Primary)

(MCB.n = 0)

(Secondary)

0 MCRB.0 W/R IOPC0

1 MCRB.1 BIO IOPC1

2 MCRB.2 SPISIMO IOPC2

3 MCRB.3 SPISOMI IOPC3

4 MCRB.4 SPICLK IOPC4

5 MCRB.5 SPISTE

IOPC5

6 MCRB.6 CANTX IOPC6

7 MCRB.7 CANRX IOPC7

MCRB.8 XINT2/ADCSOC IOPD0

9 MCRB.9 EMU0 Reserved

10 MCRB.10 EMU1 Reserved

11 MCRB.11 TCK Reserved

12 MCRB.12 TDI Reserved

13 MCRB.13 TDO Reserved

14 MCRB.14 TMS Reserved

MCRB.15 TMS2 Reserved

Notes: 1) Due to the absence of the W/R/IOPC0, BIO/IOPC1, and SPISTE/IOPC5 pins, bits 0,

1, and 5 of MCRB must be treated as reserved in the ’2402.

2) Due to the absence of SPI and CAN modules (in ’2402), bits 2, 3, 4, 6, and 7 of MCRB

should always be written with 0. The corresponding pins work as GPIO pins only.

3) Due to the absence of the CAN module and W/R

function in ’2404, bits 0, 6, and 7

of MCRB should always be written with 0. The corresponding pins work as GPIO

pins only.

4) Due to the absence of the W/R

function in ’2406, bit 0 of MCRB should always be

written with 0. The corresponding pin works as a GPIO pin only.