Specifications

I/O MUX Control Registers

5-6

Table 5–2. I/O Mux Control Register A (MCRA) Configuration

Pin Function Selected

Bit # Name.bit # (MCA.n = 1)

(Primary)

(MCA.n = 0)

(Secondary)

0 MCRA.0 SCITXD IOPA0

1 MCRA.1 SCIRXD IOPA1

2 MCRA.2 XINT1 IOPA2

3 MCRA.3 CAP1/QEP1 IOPA3

4 MCRA.4 CAP2/QEP2 IOPA4

5 MCRA.5 CAP3 IOPA5

6 MCRA.6 CMP1 IOPA6

7 MCRA.7 CMP2 IOPA7

MCRA.8 CMP3 IOPB0

9 MCRA.9 CMP4 IOPB1

10 MCRA.10 CMP5 IOPB2

11 MCRA.11 CMP6 IOPB3

12 MCRA.12 T1CMP IOPB4

13 MCRA.13 T2CMP IOPB5

14 MCRA.14 TDIRA IOPB6

MCRA.15 TCLKINA IOPB7

Note: Due to the absence of XINT1/IOPA2 and TDIRA/IOPB6 pins, bits 2 and 14 of MCRA must

be treated as “reserved” for ’2402 devices.

5.3.2 I/O Mux Output Control Register B

Figure 5–3. I/O Mux Control Register B (MCRB) — Address 7092h

15 14 13 12 11 10 9 8

MCRB.15

MCRB.14 MCRB.13 MCRB.12 MCRB.11 MCRB.10 MCRB.9 MCRB.8

RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0

76543210

MCRB.7

MCRB.6 MCRB.5 MCRB.4 MCRB.3 MCRB.2 MCRB.1 MCRB.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-1

Note: R = Read access, W = Write access, -0 = value after reset