Specifications

Design Setup
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 9
R
OPERATE
The OPERATE state monitors the FPGA_RTR. An asserted FPGA_RTR indicates that the core
is in the wrong bus mode and the FPGA needs to be reconfigured. FGPA_RTR is an input to the
CPLD design and is connected to the RTR output of the core. If FPGA_RTR asserts, then the
state machine transitions to the next state and triggers the reconfiguration sequence;
otherwise, it remains in the OPERATE state.
TRIGGER_PROG
TRIGGER_PROG is the first state of the reconfiguration sequence. Here, the state machine
waits for 300 ns while PROG_B is asserted Low to the FPGA. The FPGA requires PROG to be
asserted a minimum of 300 ns. Once this is completed, it transitions to the next state where the
new bitstream is loaded.
RECONFIGURE
During the RECONFIGURE state, the new bitstream is loaded into the FPGA. This state
monitors the FPGA_DONE input, which is the FPGA DONE pin, to ascertain when the FPGA
reconfiguration is complete.
RECONFIGURE_DONE
RECONFIGURE_DONE is the final state in the reconfiguration sequence. Once the device is
reconfigured, the bus mode should not change unless a system reset occurs, causing a
transition back to the INIT_STATE.
MANUAL_OVERRIDE
The MANUAL_OVERRIDE state is optional. It is entered if the MAN_AUTO_B input to the
CPLD design is Low. This allows users to force the bitstream revision number to be loaded
based on board jumpers or switches. The ML455 board it supports this feature prototyping or
debugging.
Generating the FORCE and WIDE Output
Once the FPGA is reconfigured, the CPLD design must store the width of the bus based on the
PCIW_EN input from the FPGA. There are two steps to setting the bus width of the newly
reconfigured bitstream, regardless of whether it is in PCI or PCI-X mode. During the
reconfiguration sequence, when the control state machine is in the OPERATE state, a register
is defined and captures the state of PCIW_EN. The value is then assigned to the WIDE output
of the CPLD design as shown in the following Verilog example code:
reg reg_wide;
always @(posedge CLK or posedge RST)
begin: wide_reg
if (RST) reg_wide <= 1'b0;
else if(state == `OPERATE)reg_wide <= PCIW_EN ;
end
assign #DLY WIDE = reg_wide;