Specifications

Design Setup

XAPP938 (v1.0) March 28, 2007 www.xilinx.com 8

PCI, and the bus actually starts in PCI-X mode, it will trigger the PROM to reconfigure the

FPGA. Otherwise, nothing will happen. Figure 4 shows the main control state machine for the

CPLD design.

INIT_STATE

INIT_STATE is the initial state after power-on or after reset is applied. From this state, the

reference design allows the user to manually override the design and force the loading of a

particular bitstream revision through board jumpers. The ML455 board supports this feature.

Otherwise, there is not a need for a transition to the Manual Override state.

Figure 4: CPLD Control State Machine

INIT_STATE

OPERATE

TRIGGER_PROG

MANUAL_OVERRIDE

RECONFIGURE_DONE

RECONFIGURE

MAN_AUTO_B = 1

FPGA_RTR = 1

MAN_AUTO_B = 0

FPGA_RTR = 0

ADVANCE_PROG = 0

FPGA_DONE = 0

ADVANCE_PROG = 1

FPGA_DONE = 1

MAN_AUTO_B = 1

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