Specifications

Design Setup
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 7
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CPLD Dynamic Configuration Design Control State Machine
The CPLD design assumes that the bus starts in either PCI or PCI-X mode. Depending on the
assumed start-up mode, the state machine reconfigures only once to the other mode when
FPGA_RTR is asserted. For example, if the CPLD design assumes the default bus mode is
Tabl e 6 : Inputs/Outputs of the CPLD Dynamic Reconfiguration Design
Signal Type Description
CLK Input PCI/
PCI-X System Clock: PCI/PCI-X clock from the PCI edge connector.
FPGA_RTR Input
FPGA_RTR: Assertion of this signal begins the reconfiguration process. This signal is
connected to the RTR output of the LogiCORE for PCI-X.
PCIW_EN Input
PCI/
PCI-X Bus Width: Bus width indicator user application output from the core for
PCI/PCI-X. When the PCIW_EN output signal is asserted, the core is operating in
64-bit mode.
MAN_AUTO_B
(1)
Input
Manual Override: Allows manual override to force bitstream selection using the inputs
FLASH_IMAGE0_SELECT and FLASH_IMAGE1_SELECT.
FLASH_IMAGE0_SELECT
(1)
Input Revision Select Bit 0: Manual override bitstream revision select bit 0.
FLASH_IMAGE1_SELECT
(1)
Input Revision Select Bit 1: Manual override bitstream revision select bit 1.
FPGA_DONE Input
FPGA Done Output: Configuration DONE pin output from FPGA. Indicates when
configuration is complete.
DOUT_BUSY Input
FPGA Busy Output: Only used for readback in Virtex-4 devices. Otherwise, driven
Low.
PROG_SW_B
(1)
Input
PROG Push Button: Onboard PROG push button to manually restart configuration of
FPGA.
PB_SW_H
(1)
Input
Board Push Button: Used as reset for FPGA and PROM to manually restart
configuration of FPGA.
EDGE_RST_I_B Input PCI/
PCI-X System Reset: PCI/PCI-X system reset from PCI edge connector.
CE Output
PROM CE Input: Tied to FPGA_DONE. When High, puts PROM into lower-power
standby mode.
BUSY Output
PROM Busy Input: Tied to DOUT_BUSY. When asserted, causes PROM to pause
configuration.
FORCE Output
Force: When asserted High, causes the core to use the WIDTH output to know the
PCI/PCI-X bus width.
WIDTH Output
Width: Indicates the bus width to the core upon reconfiguration. Setting this output to
1 indicates a 32-bit bus width, and setting it to 0 indicates a 64-bit bus width.
REV_SEL0 Output Revision Select 0: Bitstream revision select bit 0 output to the PROM.
REV_SEL1 Output Revision Select 1: Bitstream revision select bit 1 output to the PROM.
PROG_B Output
FPGA PROG_B Input: When asserted Low, the FPGA clears its configuration memory
and restarts the configuration process.
INIT_B Output FPGA INIT_B Input: Can be used to delay configuration of the FPGA.
CF Output PROM CF Input: Assertion resets PROM an initiates configuration sequence.
OE_RESET Output PROM OE/RESET Input: Holds PROM in reset when deasserted Low.
FPGA_RDWR_B Output FPGA RDWR_B Input: Indicates direction of FPGA SelectMap data bus.
FPGA_CS_B Output FPGA CS_B Input: Chip select to enable the SelectMap data bus.
Notes:
1. These ports are used on the ML455 development board. When manual bitstream selection and push buttons are not available on the board,
these ports are optional.