Specifications

Design Setup
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 6
R
Detailed information on the ML455 board is available in the Virtex-4 Development Kit User
Guide for PCI/PCI-X at: http://www.xilinx.com/bvdocs/userguides/ug084.pdf
.
The FORCE and WIDE signals are used to drive the configuration vector bits 502 and 503,
respectively. These signals are discussed in the “Design Setup” section.
Design Setup This section describes a scenario using dynamic board reconfiguration to ensure the correct
core bitstream is loaded. This design is tested using the ML455 board. “Reference Design,”
page 11 details the Virtex-4 (v5) core on the ML455 board. The design setup for using the
Virtex-5 (v4) and (v6) cores varies slightly depending on the core chosen. Most of the
differences are in the connections for the PCI-X bus mode detect and bus width manual signals
in the user application design. The same CPLD design can be used with either core.
CPLD Dynamic Reconfiguration Design Ports
When a reconfiguration is necessary, the dynamic reconfiguration design communicates with
the onboard PROM. The inputs and outputs of the design are shown in Ta bl e 6 .
Figure 3: ML455 Board Connections for Dynamic Bitstream Reconfiguration
D[0:7]
REV_SEL0
REV_SEL1
CLKOUT
To P2
From P2
CLKIN
BUSY
CF
CE
OE/RESET
D[7:0]
CCLK M0 M1 M2
CPLD_SPARE[1:10]
FORCE
WIDE
PCIW_EN
RTR
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
31
29
33
32
5
6
34
23
28
27
39
40
12 8 2
PB_SW_h
Prog_SW_b
313
1
41
43
42
8
10
2
From/
To P2
33 MHz
CPLD
CLK
DIP SW
SW5
44
Flash_Image0_Select Flash_Image1_Select
MAN_AUTO_B
X938_04_082106
State Machine
and Logic
P3
3
5
1
4
6
2
U1
Platform Flash
XCF32PF
U6
CPLD
XC2C32
U10
FPGA
XC4VLX25