Specifications

Dynamic Board Reconfiguration
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 4
R
be reconfigured. The RTR signal is also used to inform the CPLD to reload the FPGA with the
new bitstream. Tabl e 3 describes RTR and other relevant PCI-X user output signals.
This reconfiguration process must occur within 2
25
clock cycles on a PCI bus and 2
26
clock
cycles on a PCI-X bus. These values are guaranteed by the respective specification and are
called T
RHFA
in each specification. This parameter indicates the time from RST# deassertion
until the first valid configuration transaction. Because the FPGA is being configured after RST#
deasserts, no bus transactions should occur during this time. Even though the FPGA does not
see the RST# assertion, the core is guaranteed by design to present in a known good state.
Since a new design does not see a RST# deassertion on the bus, the bus width at power-up is
unknown. To resolve this problem, the core outputs PCIW_EN to indicate the initial bus width as
an input to the CPLD reconfiguration design. The CPLD remembers the state of PCIW_EN and
forces the core into the correct bus width by forcing certain inputs after the new bitstream is
loaded. Depending on the version of the core, the bus width is set in one of two ways. The
newer Virtex-5 cores have input ports to set the bus width. The bus width in the Virtex-4 core
(v5) for PCI-X is set using two bits of the 512-bit configuration vector.
Virtex-5 Cores: (v6) for PCI-X Designs and (v4) for PCI Designs
The newer cores supporting Virtex-5 designs have input ports allowing the user to set both the
bus mode and bus width (Ta bl e 4 ).
Table 3: Core Reconfiguration Output Signals for PCI-X
Signal Type Description
RTR Output RTR is an output signal used in dual configuration designs. When
RTR is asserted by the interface, the user application must
reconfigure the FPGA device with an alternate bitstream.
PCIX_EN Output When the PCIX_EN output signal is asserted High, the core is
operating in PCI-X mode.
PCIW_EN Output When the PCIW_EN output signal is asserted High, the core is
operating in 64-bit mode.
Table 4: Virtex-5 LogiCORE Reconfiguration Userapp Signals
Signal Type Description
BM_DETECT_DIS Input
Bus Mode Detect Disable: Active High. When asserted,
this signal forces the core to start in the mode indicated by
the BM_MANUAL_PCI port.
BM_MANUAL_PCI Input
Bus Mode Manual PCI: When BM_DETECT_DIS is
asserted, the
LogiCORE for PCI-X designs samples this
input to determine the operating mode. If this input is set to
1, then the core operates in PCI mode. If this input is set to
0, then the core operates in PCI-X mode. If
BM_DETECT_DIS is not asserted, then this input has no
effect on the core.
BW_DETECT_DIS Input
Bus Width Detect Disable: Active High. When asserted,
it forces the core to ignore the bus width initialization
pattern and sample the BW_MANUAL_32B input instead.
BW_MANUAL_32B Input
Bus Width Manual as 32 Bit: When BW_DETECT_DIS is
asserted, the core assumes it is plugged into a 32-bit bus
and the input is set to 1. Setting the input to 0 forces the
core to assume it is plugged into a 64-bit capable bus. If
BW_DETECT_DIS is not asserted, then this input has no
effect on the core.