Specifications

PCI-X Operation Modes

XAPP938 (v1.0) March 28, 2007 www.xilinx.com 3

PCI-X add-in cards indicate their mode and maximum speed capability using the M66EN and

PCIXCAP signals. The use of these signals is beyond the scope of this application note. For

more information on M66EN and PCIXCAP, refer to section 6.2 of the PCI-X Protocol

Addendum to the PCI Local Bus Specification v2.0a.

PCI-X Operation

Modes

The LogiCORE solution for the PCI-X standard operates in one of the following modes (each

one requires a separate bitstream):

• PCI mode only at 33 MHz

• PCI-X mode only, up to 133 MHz

• Dual mode - PCI at 33 MHz and PCI-X at 66 MHz (Virtex-II and Virtex-II Pro devices only)

The bitstreams for the different modes of operation are differentiated by using the correct

combination of wrapper, UCF, and LogiCORE files. In the majority of cases, the same user

application can work with either mode. To create two bitstreams, synthesize with different

wrapper files and implement with different UCF and core files. The reference design files

(“Reference Design,” page 11) help accomplish these tasks. For more information on the

wrapper, UCF, and LogiCORE files used to create the different bitstreams are found in

Chapter 3 of the Getting Started Guide for PCI-X delivered with the LogiCORE files.

A CPLD controls loading the correct bitstream from an onboard PROM when two bitstreams

are used for both PCI and PCI-X operation. This method is outlined below.

Dynamic Board

Reconfiguration

To support both PCI and PCI-X modes of operation, a default bitstream is loaded at power-up,

and the FPGA is configured. If the core determines it is in the wrong bus mode, a new bitstream

must be loaded. A single bitstream designed for 64-bit buses can support both 32-bit and 64-bit

PCI/PCI-X buses. The bitstreams differ only by the core’s mode of operation.

At power-up, a default bitstream is loaded into the FPGA. The bridge source on the PCI bus

drives the initialization pattern when RST# is deasserted. At this point, the LogiCORE for PCI-X

knows both the bus mode and the bus width. If the core is in the wrong mode for the bus, it

asserts the user application output signal – RTR. The RTR signal indicates that the core must

Figure 2: PCI-X Initialization Pattern

PCI_CLK

RST#

REQ64#

TRDY#

STOP#

PERR#

DEVSEL#

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