Specifications

PCI-X Device Initialization and Add-In Card Requirements
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 2
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PCI-X Device
Initialization
and Add-In Card
Requirements
PCI-X device and add-in cards must be able to recognize the PCI or PCI-X bus mode and
width. To be fully compliant, the device must adjust its operation to match the bus mode and
width dynamically. Designers are encouraged to review Chapter 6 of the PCI-X Protocol
Addendum to the PCI Local Bus Specification v2.0a for detailed information on these
requirements.
The source bridge resource indicates to the PCI/PCI-X device the bus width through REQ64#
at the rising edge of reset. If the bridge asserts REQ64# at the rising edge of RST#, it indicates
a 64-bit bus. If the host does not assert REQ64# at the rising edge of RST#, the bus is 32 bits
wide. Figure 1 shows the host indicating to all devices on the bus segment that the bus is 64
bits wide.
From the time that power is valid to the rising edge of RST#, the PCI specification guarantees
a minimum of 100 ms. This parameter is called T
PVRH
. The FPGA must configure within this
time to see the bus width and bus mode initialization pattern. For detailed information on all bus
timing parameters, see Chapter 4 of the PCI Local Bus Specification v3.0.
Along with bus-width initialization, the bridge resource must inform all connected devices of the
bus mode. In general, the choice is either PCI or PCI-X bus mode, but this can be further
segmented depending on the clock frequency. The bridge resource indicates the bus mode by
driving a certain pattern on PERR#, DEVSEL#, STOP#, and TRDY# during the deassertion of
RST#. This is similar to the method used to indicate the bus width using REQ64#. Ta bl e 2
shows a subset of the initialization pattern for PCI and PCI-X devices.
The solution for the PCI-X standard is designed to operate up to 133 MHz and does not
differentiate between the different mode patterns. The following is an example of the logic:
is_pcix_mode = PERR# and DEVSEL# and (not STOP# or not TRDY#)
By using timing analysis, designers ensure that the user application and core meet the
maximum system timing requirements.
Figure 2 is an example of a PCI-X initialization pattern along with REQ64#, indicating a 64-bit
bus.
Figure 1: PCI Bus Width Indication
PCI_CLK
RST#
REQ64#
X938_01_082106
Tabl e 2 : Initialization Pattern for PCI and PCI-X Devices
PERR# DEVSEL# STOP# TRDY# Mode
Min Clock Frequency
(MHz)
Max Clock Frequency
(MHz)
1 1 1 1 Conventional 33 MHz 0 33
1 1 1 1 Conventional 66 MHz 33 66
1110PCI-XMode1 50 66
1 1 0 1 PCI-X Mode 1 66 100
1 1 0 0 PCI-X Mode 1 100 133