Specifications

Conclusion
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 15
R
If the ML455 board is changed by applying a jumper shunt across P8 pins 2 and 3 causing
PCIXCAP to be pulled to ground, it indicates that the card is not PCI-X capable. Since the PCI
mode bitstream is only capable of running up to 33 MHz, a jumper shunt should be placed
across P9, shorting M66EN to ground. Now, powering up the system with the same design files
will result in the following:
1. Power is applied to the board and the PCI bitstream is loaded.
2. The system recognizes the board as PCI capable due to the PCIXCAP setting and starts
the bus in PCI mode.
3. The system recognizes the board supports 0 to 33 MHz PCI operation due to M66EN.
4. The core recognizes the bus is in PCI mode, which matches the loaded bitstream and does
not assert RTR to the user.
5. The device ID of the ML455 board indicates the PCI mode bitstream is loaded by showing
a value of 2222.
Various tools can be used to probe PCI configuration space. A simple one to use on a Windows
system is the PciTree tool available at: http://www.pcitree.de.
Using this tool, the device ID of
the board can be verified.
Conclusion The LogiCORE for PCI-X is capable of running in both PCI and PCI-X modes. For a PCI-X
design to be fully compliant, it must be able to operate in both PCI-X mode and PCI mode. This
application note describes how users can use a CPLD to dynamically reconfigure the FPGA to
support PCI-X and full PCI backwards compatibility in their PCI-X system when two separate
bitstreams are required – one for each mode.
References PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a
LogiCORE for PCI-X v5.0 User Guide (U
G160)
PCI Local Bus Specification, Revision 3.0
Revision
History
The following table shows the revision history for this document.
Date Version Revision
03/28/07 1.0 Initial Xilinx release.