Specifications

Reference Design

XAPP938 (v1.0) March 28, 2007 www.xilinx.com 14

The CPLD Dynamic Reconfiguration Design files are available in the directory

xapp938/Verilog/CPLD_files. This design can be implemented by creating an ISE

Project through the ISE Project Navigator targeting a XC2C32-4VQ44 device. Implementing

this project results in programming files for the ML455 CPLD. A simulation testbench and a

simulation script file for ModelSim is provided in the xapp938/<Verilog or

VHDL>/CPLD_files directory. In ModelSim, target this directory and run the

simulate_mti.do file to run the simulation.

Verification Example

Users can quickly verify the design using the ML455 board and the bitstreams provided. The

reference design was tested on different systems, including a Dell Precision 670 workstation

(with a 64-bit PCI-X slot). This section describes how to bring up the board in this Dell system

and verify the design. The easiest way to determine if the correct bitstream is loaded is by using

a PCI bus tool to read the configuration space of the board once it is powered up. For simplicity,

the configuration bitstreams each have a unique device ID as shown in Ta bl e 8 .

The device ID is located in bits 31:16 of the first DWORD in the PCI configuration header at

address 0x00. This is a simple way to verify the correct bitstream is loaded.

The CPLD design as provided assumes the bus mode will be PCI and will load the PCI

bitstream at power-up. If the bus turns out to be in PCI-X mode, then the core will notify the

CPLD by asserting the FPGA_RTR signal indicating a new bitstream needs to be loaded into

the FPGA. The CPLD will then trigger a reconfiguration process and load the PCI-X design.

Using the ML455 User Guide as a reference:

1. Program the onboard PROM to have the PCI bitstream as revision 0 and the PCI-X

bitstream as revision 1.

2. Program the CPLD with the provided CPLD bitstream.

3. Remove the jumper shunt from P8 on the ML455 board to indicate that the board is capable

of PCI-X 133 operation.

4. Plug the board into the PCI-X 133 slot and power on the system. The following steps will

then occur:

a. Power is applied to the board and the PCI bitstream is loaded.

b. The system recognizes the board as PCI-X 133 capable due to the PCIXCAP setting

and starts the bus in PCI-X mode.

c. The core recognizes it is in the wrong bus mode and asserts the RTR user application

output, which is an input to the CPLD design.

d. The CPLD reconfigures the FPGA with the PCI-X bitstream.

e. The device ID of the ML455 board indicates the PCI-X mode bitstream is loaded by

showing a value of 1111.

Table 8: Device IDs for Available Bitstreams

Bitstream Device ID

ml455_xcv4lx25_ff668_bitfile_cclk_pci.bit 2222

ml455_xcv4lx25_ff668_bitfile_cclk_pcix.bit 1111