Specifications

ManualsBrandsSimplicity ManualsLawn Mower1691468

Reference Design

XAPP938 (v1.0) March 28, 2007 www.xilinx.com 13

After the LogiCORE license is obtained, users can generate a core using the CORE Generator

tool. If the generated core file, pcix_core.ngc, is dropped into the xapp938/<Verilog or

VHDL>/v5_pcix_core_files/src/xpci directory, then the PCI-X design can be

implemented by using the run_xilinx.bat or run_xilinx.csh scripts in the

/example/xilinx/ directories. The result will be both a bit file for PCI-X and PCI for the

PROM on the ML455 board.

Figure 5: Directory Structure of Reference Design

xapp938

Verilog

example

v5_pcix_core_files

src

CPLD_files

cpld_top.jed

ml455_xcv4lx25_ff668_bitfile_cclk_pci.bit

ml455_xcv4lx25_ff668_bitfile_cclk_pcix.bit

source

synthesis

xilinx

ucf

wrap

xpci

VHDL

cpld_top.ucf

cpld_top.v

simulate_mti.do

testbench.v

wave.do

cfg_test_n.v

cfg_test_x.v

pcix_top.v

pcix_top_r.v

userapp.v

run_xil.bat

run_xil.csh

4vlx25ff668_64n.ucf

4vlx25ff668_64xf.ucf

pcix_lc_64ng.v

pcix_lc_64x.v

pcix_core.v

run_xst.bat

run_xst.csh

run_xst_pci.cmd

run_xst_pci.prj

run_xst_pcix.cmd

run_xst_pcix.prj

example

v5_pcix_core_files

src

CPLD_files

source

synthesis

xilinx

ucf

wrap

xpci

cpld_top.ucf

cpld_top.vhd

simulate_mti.do

testbench.vhd

wave.do

cfg_test_n.vhd

cfg_test_x.vhd

pcix_top.vhd

pcix_top_r.vhd

userapp.vhd