Specifications

Reference Design
XAPP938 (v1.0) March 28, 2007 www.xilinx.com 11
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LogiCORE (v4) for PCI or LogiCORE (v6) for PCI-X
The Virtex-5 cores (v4 and v6) do not use the configuration vector used by the Virtex-4 core
(v5).
The user must generate two designs resulting in two bitstreams. One bitstream is for PCI mode,
the other for PCI-X mode. For the PCI mode bitstream, the core (v6) for PCI-X can be used in
PCI 33 MHz mode, and the core (v4) for PCI can be used in PCI 66 MHz mode.
In the PCI mode bitstream, the core user application inputs BM_DETECT_DIS and
BM_MANUAL_PCI must be tied to logic 1, as shown in the following Verilog example.
// Bus Mode Detect Disable
assign BM_DETECT_DIS = 1’b1;
// Bus Mode Manual as PCI
assign #DLY BM_DETECT_DIS = 1’b1;
The PCI-X mode bitstream uses the following settings:
// Bus Mode Detect Disable
assign BM_DETECT_DIS = 1’b1;
// Bus Mode Manual as PCI
assign BM_DETECT_DIS = 1’b0;
After the bitstream is loaded, the design expects the bus to be in the mode set by these bits. If
not, the core asserts RTR to signal it is in the wrong mode. Each design must also drive the bus
width detect and bus width manual bits as follows:
// Bus Width Detect Disable
assign BW_DETECT_DIS = FORCE; // FORCE is FPGA input
// Bus Width Manual As 32-Bit
assign BW_MANUAL_32B = !WIDE; // WIDE is FPGA input
As shown in Figure 3, the signals FORCE and WIDE are inputs to the FPGA. They are
controlled by the CPLD as discussed in the section “Generating the FORCE and WIDE Output.”
In this example, WIDE is inverted because, in the CPLD example design, WIDE is High if the
bus is in 64-bit mode. The core expects the BW_MANUAL_32B to be Low if the core is in 64-
bit mode, and High if it is in 32-bit mode.
Reference
Design
The reference design files (VHDL and Verilog source code) for the CPLD are available in a
downloadable ZIP file from the Xilinx website at:
www.xilinx.com/bvdocs/appnotes/xapp938.zip
The PCI-X standard portion of the reference design files use the Virtex-4 core (v5) for PCI-X.
Designers can apply the techniques discussed in Design Setup when targeting the Virtex-5 (v4)
core for PCI or the Virtex-4 core (v6) for PCI-X. The CPLD design can be used with either core
as it is not specific to the FPGA device type.
This design is fully tested and verified on the ML455 board. The reference design also includes
wrappers for the (v5) core for PCI-X, showing the changes necessary to the configuration
vector as discussed in the section “Modifying the Core User Files.” The reference design will be
updated to include the Virtex-5 (v4) and (v6) core files when testing is complete.
ML455 Development Board for PCI/PCI-X Designs
The ML455 is a 3.3V, 64-bit board. This board is not a Universal board and must not be plugged
into 5V PCI slots. Chapter 1 of the ML455 User Guide (UG084) describes how to identify a 3.3V
system board slot.