Specifications

Design Setup
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Next, the CPLD design must only assert the FORCE output to the FPGA if a reconfiguration
occurs. In other words, the design should not force the bus width if the bus starts in the same
mode expected by the FPGA design. To accomplish this, a register is set when the control state
machine moves through the RECONFIGURE state and remains set unless a reset occurs as
shown in the Verilog example code below.
reg reg_force;
always @(posedge CLK or posedge RST)
begin: force_reg
if (RST) reg_force <= 1'b0;
else if(state == `RECONFIGURE_DONE)
reg_force <= 1'b1 ;
end
assign #DLY FORCE = reg_force;
Depending on the core being used, the user application design must be modified to use the
FPGA inputs WIDE and FORCE.
Modifying the Core User Files
LogiCORE (v5) for PCI-X Designs
When using the Virtex-4 core (v5) follow this section to set up a user application design.
The user must generate two designs resulting in two bitstreams. One bitstream is for PCI mode,
the other for PCI-X mode.
In the PCI mode bitstream, configuration bit 504 and bit 505 must be set to 1, as shown in the
following Verilog example code:
// Bus Mode Detect Disable
assign CFG[504] = 1’b1;
// Bus Mode Manual as PCI
assign CFG[505] = 1’b1;
The PCI-X mode bitstream uses the following settings:
// Bus Mode Detect Disable
assign CFG[504] = 1’b1;
// Bus Mode Manual as PCI
assign CFG[505] = 1’b0;
After the bitstream is loaded, the design expects the bus to be in the mode set by these bits. If
not, the core asserts RTR to signal it is in the wrong mode. Each design must also drive the bus
width detect and bus width manual bits as follows:
// Bus Width Detect Disable
assign CFG[502] = FORCE; // FORCE is FPGA input
// Bus Width Manual As 32-Bit
assign CFG[503] = !WIDE; // WIDE is FPGA input
As shown in Figure 3, the signals FORCE and WIDE are inputs to the FPGA. They are
controlled by the CPLD as discussed in the section “Generating the FORCE and WIDE Output.”
In this example, WIDE is inverted because, in the CPLD example, design WIDE is High if the
bus is in 64-bit mode. The core expects configuration bit 503 to be Low if the core should be in
64-bit mode and High if it should be in 32-bit mode.
Each design provides the RTR and PCIX_EN output signals to the CPLD as shown in Figure 3.