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XAPP938 (v1.0) March 28, 2007 www.xilinx.com 1

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Summary The Xilinx LogiCORE™ solution for dynamic bus mode reconfiguration of PCI® and PCI-X

designs requires a different bitstream for each mode when targeting Virtex™-4 or Virtex-5

devices. To be fully compliant, the FPGA must recognize the bus type and select the

appropriate bitstream for the core to operate in the correct mode. This application note

discusses how to dynamically reload the FPGA after power-up, using a CPLD when the initial

bitstream is not compatible with the bus mode. The reference design is fully verified and tested

using the Virtex-4 Development Kit for PCI and PCI-X designs (ML455). FPGA and CPLD

design files for this board are included in the reference design file.

Overview Xilinx offers four cores for PCI and PCI-X designs. The appropriate core choice is based on the

target device and design requirements. Each core has a primary version number (shown in

Table 1 ) followed by a revision or build number.

More information about the current versions of these cores is available in the LogiCORE data

sheets for PCI and PCI-X section of the PCI/PCI-X

lounge.

The LogiCORE products support the dynamic reconfiguration option required for PCI-X

compliance. The dynamic reconfiguration technique can be used with any PCI-X design for any

of the supported devices shown in Ta ble 1 . However, this application note focuses on Virtex-4

and Virtex-5 designs. The Virtex-4 core (v5) and Virtex-5 core (v6) have slight variations in the

user application ports. This application note describes interfacing to each of these cores to

accomplish full PCI-X compliance. The Virtex-5 core (v4) also supports the dynamic

reconfiguration option. Designers using Virtex-5 devices have the option of using the standard

core (v4) to achieve 66 MHz PCI operation and the version 6 core for PCI-X operation. Both

version 5 and version 6 of the PCI-X solution only support 33 MHz PCI operation.

Application Note: Virtex-4 and Virtex-5 Solutions

XAPP938 (v1.0) March 28, 2007

Dynamic Bus Mode Reconfiguration of

PCI-X and PCI Designs

Authors: John Ayer and Jameel Hussein

Table 1: Available LogiCORE Products for PCI-X and PCI Solutions

Core

Primary

Version

Device(s) Supported

Bus Mode

Reconfiguration

Support

PCI

Virtex-4, Virtex-II Pro, Virtex-E, Virtex,

Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II

PCI v4 Virtex-5 Yes

PCI-X v5 Virtex-4, Virtex-II Pro, Virtex-E Yes

PCI-X v6 Virtex-5 Yes

Summary of content (15 pages)

PAGE 1
Application Note: Virtex-4 and Virtex-5 Solutions Dynamic Bus Mode Reconfiguration of PCI-X and PCI Designs R Authors: John Ayer and Jameel Hussein XAPP938 (v1.0) March 28, 2007 Summary The Xilinx LogiCORE™ solution for dynamic bus mode reconfiguration of PCI® and PCI-X designs requires a different bitstream for each mode when targeting Virtex™-4 or Virtex-5 devices.
PAGE 2
R PCI-X Device Initialization and Add-In Card Requirements PCI-X Device Initialization and Add-In Card Requirements PCI-X device and add-in cards must be able to recognize the PCI or PCI-X bus mode and width. To be fully compliant, the device must adjust its operation to match the bus mode and width dynamically. Designers are encouraged to review Chapter 6 of the PCI-X Protocol Addendum to the PCI Local Bus Specification v2.0a for detailed information on these requirements.
PAGE 3
R PCI-X Operation Modes PCI_CLK RST# REQ64# TRDY# STOP# PERR# DEVSEL# X938_02_082106 Figure 2: PCI-X Initialization Pattern PCI-X add-in cards indicate their mode and maximum speed capability using the M66EN and PCIXCAP signals. The use of these signals is beyond the scope of this application note. For more information on M66EN and PCIXCAP, refer to section 6.2 of the PCI-X Protocol Addendum to the PCI Local Bus Specification v2.0a.
PAGE 4
R Dynamic Board Reconfiguration be reconfigured. The RTR signal is also used to inform the CPLD to reload the FPGA with the new bitstream. Table 3 describes RTR and other relevant PCI-X user output signals. Table 3: Core Reconfiguration Output Signals for PCI-X Signal Type Description RTR Output RTR is an output signal used in dual configuration designs. When RTR is asserted by the interface, the user application must reconfigure the FPGA device with an alternate bitstream.
PAGE 5
R Dynamic Board Reconfiguration Virtex-4, Virtex-II Pro, Virtex-E (v5) Core for PCI-X Designs The configuration file parameters used as part of a reconfiguration design are shown in Table 5. These bits are found in the 512-bit configuration vector input to the LogiCORE for PCI-X designs. Table 5: Configuration Vector Parameters Parameter Bit Description 504 Setting this bit to 1 forces the LogiCORE for PCI-X to start in the mode set by bit 505.
PAGE 6
R Design Setup U1 Platform Flash D[0:7] XCF32PF 8 D[7:0] U6 CPLD XC2C32 CE 42 BUSY 41 U10 FPGA XC4VLX25 31 FORCE 29 33 32 5 WIDE PCIW_EN RTR DONE 6 34 DOUT_BUSY RDWR_B CS_B 23 REV_SEL0 39 CLKIN REV_SEL1 40 From P2 1 3 5 P3 28 PROG_B 27 INIT_B 2 12 8 2 3 13 2 4 6 MAN_AUTO_B CLKOUT State Machine and Logic Flash_Image1_Select 44 Flash_Image0_Select OE/RESET PB_SW_h 43 Prog_SW_b To P2 CF 10 CPLD_SPARE[1:10] 1 CCLK 33 MHz CPLD CLK M0 M1 M2 From/ To P2 SW5 DIP SW
PAGE 7
R Design Setup Table 6: Inputs/Outputs of the CPLD Dynamic Reconfiguration Design Signal Type Description CLK Input PCI/PCI-X System Clock: PCI/PCI-X clock from the PCI edge connector. FPGA_RTR Input FPGA_RTR: Assertion of this signal begins the reconfiguration process. This signal is connected to the RTR output of the LogiCORE for PCI-X. PCIW_EN Input PCI/PCI-X Bus Width: Bus width indicator user application output from the core for PCI/PCI-X.
PAGE 8
R Design Setup PCI, and the bus actually starts in PCI-X mode, it will trigger the PROM to reconfigure the FPGA. Otherwise, nothing will happen. Figure 4 shows the main control state machine for the CPLD design.
PAGE 9
R Design Setup OPERATE The OPERATE state monitors the FPGA_RTR. An asserted FPGA_RTR indicates that the core is in the wrong bus mode and the FPGA needs to be reconfigured. FGPA_RTR is an input to the CPLD design and is connected to the RTR output of the core. If FPGA_RTR asserts, then the state machine transitions to the next state and triggers the reconfiguration sequence; otherwise, it remains in the OPERATE state. TRIGGER_PROG TRIGGER_PROG is the first state of the reconfiguration sequence.
PAGE 10
R Design Setup Next, the CPLD design must only assert the FORCE output to the FPGA if a reconfiguration occurs. In other words, the design should not force the bus width if the bus starts in the same mode expected by the FPGA design. To accomplish this, a register is set when the control state machine moves through the RECONFIGURE state and remains set unless a reset occurs as shown in the Verilog example code below.
PAGE 11
R Reference Design LogiCORE (v4) for PCI or LogiCORE (v6) for PCI-X The Virtex-5 cores (v4 and v6) do not use the configuration vector used by the Virtex-4 core (v5). The user must generate two designs resulting in two bitstreams. One bitstream is for PCI mode, the other for PCI-X mode. For the PCI mode bitstream, the core (v6) for PCI-X can be used in PCI 33 MHz mode, and the core (v4) for PCI can be used in PCI 66 MHz mode.
PAGE 12
R Reference Design M66EN and PCIXCAP Users must know how to set the ML455 board to indicate to the system if it is a PCI-X or PCI card. As described in Chapter 6 of the PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev 2.0, the combination of M66EN and PCIXCAP advertise the ability of the card to the system controller. The ML455 board allows users to customize the board through the following settings: M66EN – 66 MHz Enable P1.B49 is wired to two-pin header pin P9.1.
PAGE 13
R Reference Design After the LogiCORE license is obtained, users can generate a core using the CORE Generator tool. If the generated core file, pcix_core.ngc, is dropped into the xapp938//v5_pcix_core_files/src/xpci directory, then the PCI-X design can be implemented by using the run_xilinx.bat or run_xilinx.csh scripts in the /example/xilinx/ directories. The result will be both a bit file for PCI-X and PCI for the PROM on the ML455 board. cpld_top.
PAGE 14
R Reference Design The CPLD Dynamic Reconfiguration Design files are available in the directory xapp938/Verilog/CPLD_files. This design can be implemented by creating an ISE Project through the ISE Project Navigator targeting a XC2C32-4VQ44 device. Implementing this project results in programming files for the ML455 CPLD. A simulation testbench and a simulation script file for ModelSim is provided in the xapp938//CPLD_files directory.
PAGE 15
R Conclusion If the ML455 board is changed by applying a jumper shunt across P8 pins 2 and 3 causing PCIXCAP to be pulled to ground, it indicates that the card is not PCI-X capable. Since the PCI mode bitstream is only capable of running up to 33 MHz, a jumper shunt should be placed across P9, shorting M66EN to ground. Now, powering up the system with the same design files will result in the following: 1. Power is applied to the board and the PCI bitstream is loaded. 2.