Specifications

Error (OPR.ERR) output will go low illuminating the OPR PAL
Fault Indicator DS3 RED.
On the LR PAL, both the Priority Select and the Detect Any
Change circuits are reset and the Lower Raise Error (LR.ERR)
will go low illuminating the LR PAL Fault Indicator DS2 RED.
M.5.2
PWR and PTIM PALs
Refer to Figure M-5, PWR and PTIM PALs.
M.5.2.1 Turn On Request
TheTurnOnRequestfromtheLRPALisusedtostartthe
Step-Start Sequence. When the PTIM PAL receives this signal it
starts the Turn On Sequence Timer that generates a high output
TIME pulse 1.5 seconds later. This first Time pulse is sent to the
PWR PAL which tells it to go to the Ready State.
M.5.2.2 Step Start Sequence Control
The following is a shortened version of the Turn-On Sequence,
refer to the Turn On Sequence at the end of this section for a more
detailed explanation. Refer to the Step Start Sequence Chart as
needed.
When the PWR PAL is in the ready state, Time pulses from the
PTIM PAL Turn On Sequence Timer tell the Turn On Sequence
Controller in the PWR PAL to execute the next step.
The following outputs from the PWR PAL are activated in this
order:
M.5.2.2.1 KLV
This signal turns on the low voltage power supply(s) and they
begin to charge up. The high signal is also sent back to U8-6 to
tell the PTIM PAL that KLV is activated. When the +8 VDC
supply is charged up, the output of the Voltage Supply Sensing
comparitor KLVX will go high allowing the Turn On Sequence
Controller to go to the next step.
M.5.2.2.2 MODENC
This signal is sent to the Transmitter Interface and called the TX
ON ENABLE-H. It controls functions on the Modulation and
Driver Encoder boards and the Output Monitor.
M.5.2.2.3 Enable 1
This signal is used by the Controller to activate some fault inputs
connected to FGATE1 and FGATE2 in addition to clocking the
Latch PAL U-12. The high signal is also sent to U8-7 to tell the
PTIM PAL that Enable 1 is activated.
M.5.2.2.4 K1
This signal will turn on the Step Start contactor K1, and remains
high for 1.7 seconds. The high signal is also sent to U8-4 to tell
the PTIM PAL that K1 is activated. An auxiliary contact on K1
sends a high signal back to the Controller called K1X.X that
allows the Turn On Sequence Controller to go to the next step.
M.5.2.2.5 Enable 2
This signal is used by the Controller to activate some fault inputs
connected to FGATE1, FGATE2, FLT1, and the FLDBK PALs in
addition to clocking the Latch PAL U-11. The high signal is also
sent to U8-8 to tell the PTIM PAL that Enable 2 is activated.
M.5.2.2.6 K2
This signal will turn on the Run contactor K2. The high signal is
also sent back to U8-3 to tell the PTIM PAL that K2 is activated.
An auxiliary contact on K2 sends a high signal back to the
Controller called K2X.X that allows the Turn On Sequence
Controller to go to the next step.
M.5.2.2.7 Enable 3
This signal is used by the Controller to activate some fault inputs
connectedtoFGATE1andFLT1inadditiontoclockingthe
LATCH PAL U13. When Enable 3 goes high the RF Mute
generated by FGATE 1 is removed.
M.5.2.3 UNFLT
This pulse is generated after the final power-up state is achieved,
and every two seconds afterwards. It is used by the FLT1 PAL
for overload fault timing.
This completes the Step Start Sequence, and all PAL outputs
remain in this condition until loss of TOR or the FLT input is
activated.
M.5.2.4 Loss Of TOR
Response to a loss of the TOR (an OFF command or fault
condition) is independent of these inputs and the transmitter is
sequentially shut down. The Turn-On Sequence Controller and
the Turn-On Sequence Timer are reset.
M.5.2.5 K2 Overload Fault
If the K2X.X auxiliary contact signal is not received by the PWR
PAL, an internal NAND gate will generate a low K2OV signal.
This K2 Overload is sent to the FLT1 PAL and is treated as a
special Overload Fault.
M.5.2.6 Fault Input
If the Master Reset FLT line from the FLT1 PAL goes high, the
transmitter is shut down and both the Turn On Sequence Con-
troller and the Turn On Sequence Timer are reset.
M.5.2.7 Error Output
PWR ERR (PWR Error) continuously monitors the Turn-On
Sequence Controller for erroneous states.
M.5.3
Fault Input Latches
All fault inputs generated by other boards in the transmitter are
connected to either J1, J6, J7, or J8 and are applied to Fault Input
Latches U21 through U25. All faults are active low inputs,
meaning that if the input is low the fault condition is present.
The purpose of the Fault Input Latches is to hold the fault so the
Fault Handling PALs can properly respond to the input. They are
clocked by FCLK0 (Fault Clock 0) which is the 4kHz clock that
has been inverted by the FGATE1 PAL.
Once the fault input has been latched it is designated as Abbre-
viated Fault Type.X. For example, once the Predriver Fault-L
input at J6-17 is latched by U21 - it is then called PD.RF.X. From
the output of the latches, each fault type is distributed to the
appropriate Fault Handling PAL.
M.5.4
Fault Handling
As explained in the Block Diagram Description, fault types are
broken down into four categories depending upon the Controller
M-4 888-2339-002
WARNING: Disconnect primary power prior to servicing.