Specifications

pin 8 is the most significant bit (MSB). Pin 9 is a DATA READY
TTL logic output.
K.5.3
Data Latches
The digital Data Latches store the digitized audio information
while the A/D converter is performing the next conversion.When
the next conversion is completed, the LOAD OUTPUT signal
from the TIMFLT PAL clocks the data latches and stores the new
digital audio information.
U6 stores the 6 most significant bits (MSB’s), and U7 stores the
6 least significant bits (LSB’s).
A logic LOW signal to the clear the latches at Pin 1, will cause
all outputs to go LOW. All outputs will remain LOW as long as
the CLEAR input remains low, no matter what the data or clock
inputs are. The CLEAR input is normally High, and will only go
low when a timing fault has occured. The Clock input to the Data
Latches is the LOAD OUTPUT pulse. The positive-going edge
of the pulse is the Clock input, which causes the output of each
data latch to go to the same state as its input at that instant. The
outputs will then remain in that state, storing the data, until
another clock input, or until the latch’s CLEAR input goes low.
K.5.4
Buffers
Buffers provide data outputs to drive the inputs on the modula-
tion encoder board. Hex buffers U8 and U9 each contain eight
sections, When a buffer input is high (logic 1), its output is also
high, and when a buffer input is low (logic 0), its output is also
low.
K.5.5
Frequency Dividers
The frequency divider’s output at TP4, CLOCK, is the input
frequency, because the jumper plug is installed in P10-2 to 1 in
this application.
The frequency divider output goes to the TIMFLT PAL and to
the carrier detector.
K.5.6
Data Strobe
The DATA STROBE signal Clocks the data latches on the
Modulation Encoders, so that digital audio data is stored in the
Modulation Encoders after the A/D conversion is complete.
The Data Strobe signal is derived from the LOAD OUTPUT
signal from the TIMFLT PAL. When the conversion process is
completed, the LOAD OUTPUT signal is delayed 60 nanosec-
onds by DL1, and becomes the Data Strobe signal at J1-35.
Buffer U10-1 inverts the DATA STROBE signal and drives the
circuits on the Modulation Encoder board.
K.5.7
Conversion Error Logic
Conversion Error logic on the TIMFLT PAL generates a DATA
CLEAR logic signal which clears all digital data in latches U6
and U7 on the Modulation Encoder boards, and also generates a
“Conversion Error” logic input, via the data strobe, to the Con-
troller. The LOAD OUTPUT is measureable at TP3 and goes to
the CLEAR inputs of latches U6 and U7.
K.5.8
Big Step Sync
The Big Step Sync circuit produces a pulse each time a Big Step
RF Amplifier turns on. A Big Step occurs whenever one or more
of the six most significant bits (MSB’s) in the digital audio signal
changes. The Big Step sync pulses synchronize the Dither oscil-
lator on the Analog Input board, and a small amount of Big Step
signal is also added to the analog input (Audio + DC) signal at
the A/D Converter input.
K.5.9
D/A Converter
An 8-bit D/A converter is used to convert the six most significant
bits of the digital audio signal back into an analog signal. The
D/A converter output, at U15-4, is a zero to -1 Volt signal, made
up only of Big Steps.
Switch S1 is provided for use in other transmitters. Both sections
of S2 are open in the DX100-3F.
The output of the D/A converter is amplified by U16-U18.
Low-pass filter R39-C49 removes any sample frequency and
other high frequency components. A small stepped “big-step
sync” signal which is added, through R70, to the Analog Input
Signal. R41 and C81 form a differentiator, which produces a
pulse each time a Big Step transition occurs. The pulses can be
observed at the output of U19 at TP21, BIG STEP SYNC. The
output signal from U19 goes to the Dither Oscillator circuit on
the Analog Input board.
K.5.10
D/A Converter/Audio Reconstruction Filter
The 12-bit digital audio signal is converted back to an analog
signal in by D/A converter circuit U11. The unfiltered D/A
converter circuit’s output is at U12-7, and is available for viewing
at test point TP9. The unfiltered output at TP9 includes a DC
component, and at full power with 100% modulation varies
between zero and about +5 Volts. At lower power levels and/or
lower modulation levels, the maximum signal amplitude at TP9
will be smaller.
The Reconstruction Filter is a low-pass filter which passes the
audio components and removes the higher frequency compo-
nents in the “steps,” effectively smoothing the output. Two
620-Ohm resistors, R19 and R22, are the terminating resistances
at the input and the output of the filter. Operational amplifier U12
drives the A/D output meter position on the Control Multimeter,
and Reconstructed audio is present at TP19.
K.5.11
Power Supplies
Three regulated voltages are provided by on-board regulators.
Each regulator circuit is fused and transient protected.
a. U20isusedasa-15Voltregulator.
b. U21 provides a +15 olt output and U23 provides a +5 Volt
output.
DC supply inputs to the A/D Converter are +22 Volts, -22 Volts,
+ 8 Vo lts a n d - 8 Volts .
Each of these is from the low voltage power supply. The inputs are
fused with 2A fuses F1, F2, F3 and F4 and regulated to +15, -15,
+5 and -5 Volts using regulators U21, U22, U23 and U24, respec-
tively.Eachregulatoroutputhas a greenStatusLED that lightswhen
888-2339-002 K-3
WARNING: Disconnect primary power prior to servicing.