Specifications

buffer amplifier goes to a Carrier Detector and the A/D PAL. The
Divideris not being used in this application. The Carrier Detector
will send a fault signal to the A/D PAL should no RF signal be
present.
K.4.2
(Audio + DC) Flow
The (Audio + DC) signal from the Analog Input is buffered by a
Buffer amplifier and sent to the A/D Converter. Theanalogsignal
is sampled approximately once every two microseconds (the
sampling rate depends on the transmitter frequency) and con-
verted into a 12-bit digital audio signal by a high-speed analog
to digital (A/D) converter. A Buffer amplifier is also driven by
the (Audio + DC) and its output is called A/D Input. It is sent to
the Control Multimeter for testing purposes.
K.4.3
A/D Converter
The A/D Converter and the A/D PAL operate in sync with each
other. (Audio + DC) from the Buffer and a Start Encode signal
from the A/D PAL allows the A/D Converter to convert the
instantaneous (Audio + DC) analog signal to a 12 Bit digitalword
that digitally represents the analog signal. When the A/D Con-
verter has finished the conversion process, it sends a Data Ready
signal back to the A/D PAL and the 12 Bit digital word is present
at the 12 outputs B1-B12 of the A/D Converter.
K.4.4
Latches And Buffers
The12 Bit digital word is transferred into the Latches by the Load
Output signal from the A/D PAL. Data Latches store the digital
data after each conversion and hold the data until the next
conversion is completed. These 12 data lines are sent to Buffers
and applied to each Modulation Encoder.
K.4.5
A/D PAL
The A/D PAL accepts the A/D Sample Pulse from the Divider
and provides the A/D Converter with Start Encode signals. When
the conversion process is finished by the A/D Converter, a Data
Ready pulse is sent back to the A/D PAL.
A Load Output from the A/D PAL is used to transfer in the 12
Bit digital word into the Latches.
A Data Strobe output from the A/D PALis invertedby an Inverter
and applied to each Modulation Encoder to latch in the current
12 Bit digital word.
The A/D PAL also monitors the timing sequence described above
and can generate an RF MUTE, Conversion Error, or stop the
Start Encode signals if a carrier loss or supply fault is detected.
K.4.6
D/A Outputs
A full 12 Bit digital word is applied to a D/A Converter which
converts the digital word back into a analog signal. The output
after passing through a Reconstruction Filter (Audio + DC) is
present at the output of the filter. The reconstructed signal is
Bufferedand sent to the Control Multimeter position labeled A/D
OUTPUT. This meter position is used for troubleshooting pur-
poses.
A second D/A Converter accepts the 6 most significant Bits
B1-B6 and converts this partial digital word into pulses. These
Big Step Sync pulses are Buffered and sent to the Analog Input
board to trigger the Dither Oscillator.
K.4.7
Power Supplies
The Voltages +22VDC, -22VDC, +8VDC and -8VDC are regu-
lated to +15VDC , -15VDC, +5VDC and -5VDC respectively.
The resulting regulated voltages are used to power circuits on
this board.
A Supply Fault Sense circuit monitors these supplies and can
generate a Supply Fault for the A/D PAL and the Controller.
K.5 Detailed Circuit Description
Referto the schematic diagram fortheA/D Converter(839-7930-
009) for all descriptions in this section.
K.5.1
Analog Input
The A/D converter analog input signal, at J4-10, is the (Audio +
DC) from the Analog Input board. The DC component deter-
mines the unmodulated transmitter power output by turning on
the required number of Big Step RF Amplifiers via the Modula-
tion Encoders. Typically 66 Big Steps RF Amplifiers are turned
on at 100 kilowatts).
The analog signal level at the board’s input is high so that
inverting amplifier U28 has a gain of less than 1 to provide the
proper signal level to the A/D Converter.
A very small amount of “BigStepsync” is added to the input
signal at the inverting input of U1 (pin 2, via R5). When a Big
Step RF Amplifier turns on, a small amount of the Big Step Sync
component forces the input to the A/D higher. This is sufficient
to ensure that the A/D Converter will not switch back to the
previous step.
K.5.2
A/D Converter
A high-speed 12-bit analog to digital converter is used in the
transmitter. The analog input voltage range is 0 to +5 Volts. An
input of zero Volts gives a digital output of “0000 0000 0000.”
An input of +5 Volts gives an output of “1111 1111 1111".
The Analog to Digital converter has two signal inputs, an analog
signal input at pin 22, and a TTL logic START CONVERT input
at pin 18. The conversion is started by the Start Convert pulse.
K.5.2.1 A/D Converter Timing
The Start Encode pulse at TP2 (see plots and A/D Timing
Sequence) goes high for 840nS and then returns low. The DATA
READY pulse at TP3 that is normally high, goes low 528nS after
the START ENCODE signal. The DATA READY remains low
for 140nS. The DATA STROBE which is an inverted output of
U5-15 at U10-2 is normally high. 564nS after the START EN-
CODE the line goes low for 140nS. The LOAD OUTPUT is
normally low and it goes high for 140nS, about 624nS after the
START ENCODE signal.
The twelve TTL level output lines are at pins 1 through 8 and 37
through 40. Pin 37 is the least significant binary bit (LSB), and
K-2 888-2339-002
WARNING: Disconnect primary power prior to servicing.