User guide

2: Software Development for the ICP
DC 900-1338I 49
8 and read register 8 (the transmit and receive data buffers) are accessed directly
through the channel’s data register. All other registers except Read and Write registers
(RRO and WRO) are accessed through the channel’s control register in two steps: a
write to select the actual register number, followed by a read or write to transfer the
data. RRO and WRO are accessible with a single transfer.
Note
These two steps must be done at CPU level 6 to lock out any ISRs
that might need to access the SCCs.
Refer to the Serial Communications Controller User’s Manual (Zilog) for SCC program-
ming instructions. The sample protocol software package includes examples of SCC
programming for asynchronous, byte synchronous, and bit synchronous communica-
tions. See Chapter 6 for more information. Also see pointer array Z8530
*scc[] in
freeway/icpcode/proto_kit/src/spsstructs.h.
2.6.3 Programming the DMA Controller
The 32-channel direct memory access (DMA) controller is programmed using a single
byte-wide command register and, for each channel, a 32-bit memory address register
and a 32-bit terminal count register. Channels 0 through 15 are dedicated to receive
operations on serial ports 0 through 15, and channels 16 through 31 are likewise dedi-
cated to transmit operations.
The command register is located at address 0x10000000. The memory address registers
begin at address 0x400FFF00. The terminal count registers begin at address
0x40xFFF80. (x is 0 for a 1 MB ICP, 3 for a 4 MB ICP, or 7 for a 8 MB ICP.) Only the
low-order 20 bits of the memory address and terminal count registers are valid, allow-
ing an address range of 1 megabyte beginning at the base address of RAM
(0x40000000). Also see pointer array
IO_DMA io_dma[3] in freeway/icpcode/
proto_kit/src/spsstructs.h
.