User guide

4 DC 900-1338I
Protocol Software Toolkit Programmer Guide
2.4.1 Processor Privilege States........................... 37
2.4.2 Stack Pointers................................. 37
2.4.3 Exception Vector Table............................ 39
2.4.4 Interrupt Priority Levels........................... 41
2.5 ICP2424 and ICP2432 Hardware Device Programming ............. 42
2.5.1 Programming the 68340/68349 ....................... 43
2.5.2 Programming the Integrated Universal Serial Controllers......... 44
2.5.3 Programming Sipex’s Multi-Mode Serial Transceivers........... 44
2.5.4 Programming the Test Mode Register.................... 45
2.5.5 Programming the LED Register (ICP2424 only) .............. 45
2.6 ICP6000 Hardware Device Programming..................... 45
2.6.1 Programming the Multi-function Peripheral................ 46
2.6.2 Programming the Serial Communications Controllers........... 48
2.6.3 Programming the DMA Controller .................... 49
3Memory Organization 51
3.1 ICP2424....................................... 51
3.2 ICP2432....................................... 53
3.3 ICP6000....................................... 54
4 ICP Download, Configuration, and Initialization 57
4.1 Download Procedures............................... 57
4.1.1 Freeway Server Download Procedure.................... 57
4.1.1.1 Downloading Without the Debug Monitor.............. 59
4.1.1.2 Downloading With the Debug Monitor................ 63
4.1.2 Embedded ICP Download Procedure.................... 64
4.1.3 ICP Buffer Size................................ 64
4.2 OS/Impact Configuration and Initialization................... 65
4.2.1 Configuration Table............................. 72
4.2.2 Task Initialization Structures......................... 72
4.2.3 Task Initialization Routine.......................... 74
4.2.4 OS/Impact Initialization........................... 74
4.3 Determining Configuration Parameters...................... 75
4.3.1 OS/Impact Memory Requirements..................... 75
4.3.2 Configuration and System Performance................... 77
4.3.2.1 Number of Configured Task Control Structures........... 78