User guide

DC 900-1338I 189

Appendix

Application Notes

This appendix clarifies some points made in the technical manuals and describes some

peculiarities of the devices and the ICP6000 hardware.

• When the Force Hardware Reset command (bits 6 and 7 of SCC write register 9)

is issued to either channel of the SCC, both channels are reset.

• When programming in a high-level language, be sure that your compiler’s opti-

mizer handles the special requirements of device-level programming correctly.

For example, if you program two writes to a hardware register in sequence, the

optimizer could inappropriately remove the first write instruction as superfluous.

• A write to mailbox 15 (ICP6000) generates a level 3 interrupt and normally enters

the PTBUG debugging tool. However, if the ICP software is “hung” with the

interrupt mask level set to three or higher, the PTBUG interrupt cannot be ser-

viced and the ICP must be reset. It is not possible to disable transmit interrupts on

the DMA controller. Receive interrupts can be disabled through a bit in Control

• During processing of an SCC interrupt, the pending interrupt must be cleared in

both the MFP, with a write to register ISRA or ISRB, and the SCC, with a write to

SCC, you must continue processing SCC interrupts (without returning from the

interrupt service routine,

S_IRET) until the MFP register GPIP or SCC read

requesting 3 A (RR3A) port shows no pending interrupts for the SCC in question.