User guide

6: ICP Software
DC 900-1338I 113
is set to the number of bytes in the block, including the header and the two-byte CRC,
if enabled. The CRC is calculated and appended to the data at the task level.
For receive, the SCC or IUSC is initially set up to generate interrupts on every character
received. Each character is compared to the configured start character. After the start
character has been found, the remainder of the BSC header can be received. The DMA
transfer count is set to the value specified in the BSC header, SCC or IUSC receive inter-
rupts are disabled, and DMA is used to receive the remainder of the message.
The following interrupts are processed in BSC mode:
SCC or IUSC Receive Character Available While enabled, this interrupt is generated
on every received character. No data is transferred to the receive buffer until the
data count is received. When the entire three-byte header has been received, the
interrupt service routine disables receive and special receive condition interrupts,
sets the DMA transfer count according to the
count field of the BSC header (plus
two if CRC is enabled), and initiates DMA transfer.
SCC or IUSC Special Receive Condition While enabled (before and during reception
of the BSC header), this interrupt is generated on receiver overrun errors. An
error count is incremented and the receive is aborted.
SCC DMA Receive Terminal Count or IUSC End of Buffer This interrupt is generated
when the data portion of a BSC message has been received. The interrupt service
routine re-enables SCC or IUSC receive and special receive condition interrupts
and restarts the receiver using the next buffer in the link-to-board queue. CRC, if
enabled, is checked at the task level.
SCC DMA Transmit Terminal Count or IUSC End of Buffer This interrupt is gener-
ated at the end of a transmitted frame. The interrupt service routine processes the
end of the transmission. (The next transmission is started at the task level.)