User`s guide

A: Line Control Procedures
DC 900-1339H 107
Table A–2 defines the EIA-232 clock signals used by the FMP software.
A.5 Idle Line Condition
When no data is being transmitted on a full-duplex circuit, the transmit line is held in
a marking condition (all one-bits are transmitted).
Table A–2: EIA-232 Clock Signals
Signal Pin Direction Description
XMT CLK 15 Input External clocking: transmit clock
Internal clocking: not used
RCV CLK 17 Input External clocking: receive clock
Internal clocking: receive clock
EXT CLK 24 Output External clocking: not used
Internal clocking: server-generated
Clock signal to be connected to the XMT CLK of the
local interface and the RCV CLK pin of the remote
interface.