User`s guide

106 DC 900-1339H
FMP Programmer’s Guide
A.3 Modem Control Lines
Table A–1 lists the EIA-232 modem control lines used by the FMP software.
A.4 Clock Signals
The FMP communication interface is designed to use either externally or internally
generated clock signals. Clocking is selected through the clock source option
(Section 4.2 on page 69). The FMP software always uses receive clocking provided by
the receive data source. Under external clocking, FMP receives its transmit clocks from
the remote computer. Under internal clocking, the transmit clock is internally gener-
ated and also output to the remote computer. You must also set the hardware clock
jumper for each link. Refer to the Freeway ICP6000R/ICP6000X Hardware Description
manual. If you need to set internal clocking, call the Simpact customer support number
given in the Preface. For the Freeway 1000, refer to the ICP2424 Hardware Description
and Theory of Operation.
Table A–1: EIA-232 Modem Control Lines
Signal Pin Direction Description
RTS 4 Output For half-duplex, RTS is turned on just before trans-
mission is started and turned off when transmission
is complete.
CTS 5 Input CTS is checked after RTS is turned on but prior to
transmit. If CTS is on at this point, transmit is
started and further changes in the CTS pin are
ignored until the next block is ready to be transmit-
ted. If CTS is off at this point, transmission is delayed
until the CTS pin is turned on.
DSR 6 Input DSR is monitored by the protocol software, and its
status is reported in the link status report.
DCD 8 Input DCD status is reported in the link status report.
DTR 20 Output DTR is turned on when the link is started and turned
off when the link is stopped.