Service Manual

PAGE 32 TECHNICAL DESCRIPTION
62 Audio Input 1 to Codec C2 (U52) prior to being converted
from single-ended to differential
Audio Signal
63 SPI_CLK 3.3V Digital
64 5V Bias for 10V Op Amps D.C.
65 Audio Output 2 from Codec C2 (U52) after passing through
1
st
Op-Amp stage
Audio Signal
66 Analogue 3.3V A3V3 D.C.
67 Analogue Ground AGND D.C.
68 Analogue 2.5V Supply Rail (Bias for 5V Op Amps and ADC)
A2V5
D.C.
69 Codec Select Strobe CODSE generated by DSP PF4 3.3V Digital
70 Digital 5V supply rail (used by 3.3V Switched Mode Power
Supply) 5V0D
D.C.
71 Analogue 5V Supply Rail (used by ADC and 5V Op Amps)
A5V
D.C.
72 Codec Reset CODRST_N generated by DSP PF5 3.3V Digital
73 Digital Ground DGND D.C.
74 Pin 23 of P5 Rx Radio Header
75 Pin 21 of P5 Rx Radio Header
76 Pin 3 of P5 Rx Radio Header
77 I2C Data (I2C_SDA) 3.3V Digital
78 Analogue 2.5V Supply Rail (Bias for 5V Op Amps and ADC)
A2V5
D.C.
79 Digital Ground DGND D.C.
80 Pin 23 of P6 Tx Radio Header
81 Pin 21 of P6 Tx Radio Header
82 Pin 3 of P6 Tx Radio Header
83 TX_PTT inputted to DSP PF15 3.3V Digital
84 I
2
C CLK (SCL) 3.3V Digital
85 Pin 20 of P5 Rx Radio Header
86 3.3V Digital Voltage Supply 3V3 D.C.
87 RX_EXTOUT inputted to DSP PF9 3.3V Digital
88 Pin 6 of P6 Tx Radio Header
89 Digital Ground DGND D.C.
90 PSTN Tx+ Audio Signal
91 Network Processor Oscillator Tri-State Enable 3.3V Digital
92 PSTN Rx- Audio Signal
93 PSTN Tx- Audio Signal