User Manual

SDB670 – SERVICE MANUAL TNM-M-E-0032
May 13 Page 35 TECHNICAL DESCRIPTION
reduced by approximately 20 dB in a single step when D415/D416 are turned on by the FPGA via
RX-GAIN.
The output of the AGC circuit contains a matching network for the following crystal filter Z401,
which in turn is matched to a dual current amplifier U402. The crystal filters provide part of the
required selectivity for rejection of close in unwanted signals.
The current amplifier provides an unbalanced to balanced conversion as well as providing a low
source impedance suitable for driving the following DAC U401. The filter comprising L485a/L486a
and associated components provides correct matching to the IF ADC.
5.3.2.3 IF Analogue to Digital Convertor
The 45 MHz balanced output from the IF stages is fed to U401 pins 1 and 2 where it is directly
clocked in via a 21.6 MHz clock at pin 9. This converts the 45 MHz analogue signal to 12 bit digital
outputs ADC-0 to ADC-D11. In addition, dither inputs are also provided in parallel with the IF input
via shaping filter L490/L491 and associated components. The dither inputs are derived from the
FPGA as 48 kHz triangular waveforms at a level such that improved resolution of the least
significant ADC bit can be obtained, effectively resulting in a reduction of at least 40 dB to the
measured noise floor, thereby enabling the measurement of a much lower level of IF signal.
Suitable high frequency roll-off is provided on all the digital outputs to minimize noise. In addition,
a 1.5 V reference voltage is derived from U401-31 which is used for biasing its analogue inputs
and also to provide low impedance current limited source voltages 1V5-S and 1V5-REF via U400.
The 12 bit digital outputs running at a 21.6 MHz sample rate are fed to the FPGA U300 where they
are processed to form I/Q quadrature signals running at a 96 kHz sample rate. This is then fed
through a series of digital filters to provide the final stage of adjacent channel filtering, after which it
is fed to the DSP U203 via the EMIF bus.
5.3.3 Transmitter
Refer to Figure 10 (page 42) and Figures 8 and 12 in TNM-S-E-0005, SDM600 Series – Issue 4
Circuit Diagrams [2].
5.3.3.1 Drivers and PA Stages
The VCO provides approximately 7 dBm output that is switched to the Tx Buffers via T/R switch
comprising D700 and D701. Tx buffers Q501 and Q502 increase the VCO level to provide
approximately 17 dBm of drive power to the Tx driver Q500. The Tx driver stage then typically
provides 16 dBm of drive to the PA module. Inter-stage attenuator networks are provided between
all amplifier stages to provide a high degree of isolation of the VCO from the Tx output.
PA module U505 utilises three Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
stages (UHF) and two MOSFET stages (VHF) to achieve the required RF output power up to a
level of +44 dBm (25 Watts).
The gain of the PA module is controlled by the power control loop to ensure that Tx output power
remains within defined limits over supply voltage and temperature extremes.
Note.
Care should be taken during servicing for low output power. If the drive power is lost,
the power control voltage will go high, which may cause the current or power into the
PA to exceed its specification. Therefore, the power supply current should be
monitored at all times and preset to as low as required. The radio has additional
inbuilt safeguards, but these should not be relied on.