User Manual
SDB670 – SERVICE MANUAL TNM-M-E-0032
May 13 Page 34 TECHNICAL DESCRIPTION
downloads the DSP and FPGA software from Flash Memory to their internal RAMs for faster
program execution and access to data. All software, except for the customer configuration, is
loaded by the factory into the Flash Memory and can be updated via the SDM600/SDP600 Code
Loader connected to external interface connector S3. DSP software comprises Boot code and
Application code, while FPGA code comprises FPGA code and MCP code. High-level software
comprising Operational Code and Customer Configuration is loaded at distribution centres and is
loaded via the SDM600/SDP600 Field Personality Programmer (FPP).
5.3.2 Receiver
Refer to Figure 10 (page 42) and Figures 7 and 11 in TNM-S-E-0005, SDM600 Series – Issue 4
Circuit Diagrams [2].
5.3.2.1 Front End Filters and RF Amplifier
The Rx input signal from the antenna passes through the harmonic filter and antenna switch. With
the mobile in receive mode, diodes D500, D5502 and D503 in the antenna switch are reverse
biased allowing the Rx input signal to be coupled through to the Rx front-end with minimal loss.
The overall insertion loss of the harmonic filter and switch is approximately 0.8 dB.
A noise blanker is also fitted to E0 band radios. The noise blanker samples the received signal
and gates the 45 MHz signal in the Intermediate Frequency (IF) stage in the event that high level
noise transients are received. Due to inherent time delays in the bandpass filters prior to the
blanking gate, gating synchronisation occurs before the transients can adversely affect the
following stages.
Varactor-tuned bandpass filters at the input and output of the RF amplifier provide Rx front-end
selectivity. Varactor tuning voltages are derived from the alignment data stored in the radio. The
DSP processes this data to optimise front end tuning relative to the programmed channel
frequencies, which may be changed at any time without re-aligning the radio.
To achieve the required varactor tuning range, an arrangement of positive and negative bias power
supplies is used to provide a total bias across the varactors of up to 14.0 VDC. A fixed 1.6 V
positive bias derived from the 3.2 V supply and voltage divider R438/R439 is applied to the
cathodes of the varactor diodes. The negative bias supplies are derived from –12 V and controlled
by the FPGA, which outputs PWM for the four front-end tuning voltages RX-TUNE1 to 4, for the
particular channel frequency selected. The PWM signal is dependent on channel frequency and
tuning and passes through level shifting transistors Q403 to Q410 where it is converted to a
negative voltage in the range –0.5 V to –11.5 V. The –12 V rail of the level translators is generated
by U908A/B/F with D912 to D915 providing the required voltage multiplication.
The RF amplifier stage comprises a low noise transistor amplifier Q402, which is compensated to
maintain good linearity and low noise matching, and Q400/Q401 provide it with a constant current
source. This provides excellent intermodulation and blocking performance across the full operating
range. The overall gain of the front-end is typically 14 dB for all bands. D412 provides protection
for Q402 from high level signals.
5.3.2.2 Mixer and IF Section
The output of the last front-end bandpass filter is coupled into a double balanced mixer comprising
T471/D470/T472, which converts the RF signal to an IF frequency of 45 MHz. The local oscillator
injection level from the Voltage Controlled Oscillator (VCO) is typically +7 dBm at TP414 with low
side injection used for UHF bands and high side for frequency bands less than 400 MHz.
Following the mixer is crystal filter Z400, its matching networks and IF amplifier Q419. The IF
amplifier provides approximately 20 dB of gain, and drives an AGC circuit comprising D413/D414.
The purpose of the AGC circuit is to linearise the Rx gain across the band as well as limiting very
high level signals that could reduce the Rx performance. The AGC is set via RX-AGC during radio
alignment and is controlled via a PWM output from the FPGA. The gain of Q419 can also be