User Manual

SDB670 – SERVICE MANUAL TNM-M-E-0032
May 13 Page 33 TECHNICAL DESCRIPTION
• DSP clock dither.
• Rx muting control.
• RSSI/Automatic Gain Control (AGC) control.
• Tx/Rx switching and Press (Push) To Talk (PTT) control.
• Synthesiser Fast-Lock control.
• Phase Locked Loop (PLL) lock detect.
• Rx/Tx Audio switching.
• Power On/Off control.
• Interface functionality with Option Boards and External Devices.
• Battery voltage, reset and Tx current monitor.
• LED status indicators.
• Software upload from Flash.
• Update Flash variables.
• RAM read/write.
• Software security.
5.3.1.2 DSP Clock Oscillator
SYN-FCLK1 is routed to DSP U203-F2 via Clock Amplifier Q201 and Clock Spread-Spectrum
circuit comprising D205 and associated components. The Clock Spread-Spectrum circuit is
incorporated to reduce the coherent 21.4 MHz frequency component by utilizing a spread spectrum
technique. This is achieved by driving varactor diode D205 with a noise source derived from an
FPGA Pulse Width Modulated (PWM) noise signal. This phase modulates the 21.6 MHz signal
with noise so that it covers a wider spectrum, thereby reducing its narrow band power level. The
output of the Spread-Spectrum circuit is amplified and squared up by Inverter U208 prior to
clocking the DSP.
5.3.1.3 Analogue Inputs and Outputs
The FPGA must supply several analogue signals to control the radio including radio tuning and
control. It does this with a separate PWM output for each function.
For example, the front-end tune signals (RX-TUNE1 to RX-TUNE4) originate from the FPGA in the
form of PWM signals, which are then integrated to provide variable low noise DC voltages. The
values for these outputs are stored in flash memory from radio alignment or hard coded into radio
software. They are selected depending on the channel that the radio is currently tuned to.
Other analogue PWM derived signals used include Tx power (PA-TXPWR), current limit (PA-ICAL)
Rx AGC voltage (RX-AGC), AFC (SYN-AFC1), VCO ALC (SYN-ALCSET), varactor bias (SYN-
VARSET), ADC dither (RX-DITHER+/-) and clock spread spectrum (CLK-SS).
Four Analogue to Digital Converters (ADCs) in the DSP, two of which are multiplexed by an
Analogue MUX U205, monitor analogue inputs. This provides a total of ten analogue inputs that
can be monitored, the main ones being PA-ISENSE, PA-TEMPSENSE, PA-TXMON, BAT-SENSE,
VCO-BIAS, LOOP-VOLTS, EXT-SENSE.
5.3.1.4 Flash Memory
Flash Memory U204 contains 64 Megabits of storage. It contains all the radio operating software,
alignment database, customer configuration and necessary status variables. When power is off, all
program software and data are retained in Flash Memory. At power-on, a boot program