SIM8300G-M2 Hardware Design V1.01 Draft

SIM8300G-M2 Hardware Design V1.01
www.simcom.com
33
/
77
Table 18: Definition of PCIe interface
Pin name
Pin
no.
Electrical
description
Functional description
Comment
PETn0
41
AO
PCIe transmit data negative
PETp0
43
AO
PCIe transmit data positive
PERn0
47
AI
PCIe receive data negative
PERp0
49
AI
PCIe receive data positive
REFCLKN
53
AIO
PCIe reference clock
negative
REFCLKP
55
AIO
PCIe reference clock
positive
PERST#
50
DI
PERST# is a functional reset
to the Add-In module
active low
3.3V voltage
domain,
CLKREQ# and
PEWAKE# required
pull up external,
Default as EP mode.
If unused, please
keep open
CLKREQ#
52
DIO
PCIe reference clock request
signal
active low
PEWAKE#
54
DIO
PCIe wake up signal
active low
Table 19: PCIe interface recommended TVS diode list
No.
Manufacturer
Part number
Package
1
WILL
ESD5302N-3/TR
DFN1006-3L
PCIe interface layout guidelines:
 Require differential trace impedance is 90±10% Ω.

The intra-lane length mismatch of the differential signal lanes is less than 700um.

Gap from other signals keeps 4xline width.

Gap between Rx-to-Tx keeps 4xline width.

Should be routed away from sensitive signals.

The TVS diode should be placed close to the PCIe pins of M.2 connector.