Hardware Design

Smart Machine Smart Decision
SIM8200EA-M2 card Hardware Design _V1.01 9 2019-06-27
1.2 Hardware Block Diagram
The Block Diagram of SIM8200EA-M2 is shown as below:
High Speed
Interface
I2C
NAND 4Gb
LPDDR4X 4Gb
MCP
8-bit
NAND
16-bit
LPDDR4X
USIM x2
PCIE GEN 3.0
32kHz
SPMI
38.4MHz
XO
QLINK_EN_0
QLINK_REQ_0
WMSS_RESET_
0
BB
5GNR/4G/3G
Modem
MODEM+Audio
DSP
Processor
Qualcomm
Location Gen 9V4
Baseband
Modem
Transceiver
RF Front End
RF
Switch
ANT2
GRFC’S
RFFE’S
MMPA/
LPAF/
LPAMIDs
QDM
Module
SIM8200EA-M2
ANT0
ANT1
VBAT__3.3v
GND
POWER
PMU
Power System&
Clock System
System
RAM+ROM
USB2.0
RESET
FULL_CARD_POWER_OFF_N
Low Speed
Peripherals
(All can be
configured as
GPIOs)
UIM Interface
(2.85V/1.8V)
DPR
GPIOs
WOWWAN
COEX
GPIOs
QLINK_0
ANTCTL0~3
Control
Signal
W_Disable1_N
W_Disable2_N
LED_1
CONFIG0
CONFIG1
CONFIG2
CONFIG3
USB3.1
PCM/I2S
PMU
BBCLK
19.2MHz
Sleep CLK
32kHz
38.4MHz
One On Chip eSIM
RF PMU
Supplies
Pa sense
4G+5G(sub-6 GHz)RF
RFFE’S
Tx/Rx
GRFC’S
RFCLK1
QLNA
Tuner
Diplexer/
N-Plexer
ANT3
ANT4
ANT5
Cotex-A7
Application processor
subsystem
RPMh Cotex-M3
M.2 KEY-B 75PIN INTERFACE
Figure 1: Standard Module block diagram
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