Hardware Design

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SIM8200EA-M2 card Hardware Design _V1.01 29 2019-06-27
3.10.1 I2S timing
Module supports 48 KHz I2S sampling rate and 32 bit coding signal (16 bit word length), the
timing diagram is showed as following:
Figure 15: I2S timing
Table 14: I2S timing parameters
3.10.2 I2S reference circuit
The following figure shows the external codec reference design.
Signal Paramete
r
Description Min. Typ. Max. Unit
I2S_MCLK
Frequency
Frequency
–
12.288
12.288
MHz
T Clock period 81.380
81.380
– ns
t(HC) Clock high 0.45T – 0.55T ns
t(LC) Clock low 0.45T – 0.55T ns
I2S_CLK
Frequency Frequency 8 48 48 KHz
T Clock period 20.83 20.83 125 us
t(HC) Clock high 0.45T – 0.55T ns
t(LC) Clock low 0.45T – 0.55T ns
I2S_WS
t(sr) DIN/DOUT and WS input setup time 16.276 – – ns
t(hr) DIN/DOUT and WS input hold time 0 – – ns
t(dtr) DIN/DOUT and WS output delay – – 65.10 ns
t(htr) DIN/DOUT and WS output hold time 0 – – ns
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