Hardware Design
Table Of Contents
- Contents
- Table Index
- Revision History
- 1 Introduction
- 2 Package Information
- 3 Interface Application
- 4 Antenna Interfaces
- 5 Electrical Specifications
- 6 Top and Bottom View of Module
- 7 Label description Information
- 8 Packaging
- Appendix
Smart Machine Smart Decision
SIM8200EA-M2 card Hardware Design _V1.01 16 2019-06-27
USB3.1-Tx+ 31 AO USB3.1 transmit data plus
480Mbps data rate.
USB3.1-Rx- 35 AI USB3.1 receive data minus
USB3.1-Rx+ 37 AI USB3.1 receive data plus
PCIe interface
PETn0 41 AO
PCIe TX Differential signals
Negative
Support PCIe GEN 3.0,
up to 8Gbps data
rate.
If unused, please keep
open.
PETp0 43 AO
PCIe TX Differential signals
Positive
PERn0 47 AI
PCIe RX Differential signals
Negative
PERp0 49 AI
PCIe RX Differential signals
Positive
REFCLKN 53 AIO
PCIe Reference Clock signal
Negative
REFCLKP 55 AIO
PCIe Reference Clock signal
Positive
PCIE assistant interface
PERSTR# 50 DI
PCIe reset signal,active low
3.3V voltage domain,
If unused, please keep
open.
CLKREQ#
52 DIO
PCIe clock request signal,active
low
PEWAKE#
54 DO
PCIe walk up signal,active low
USIM interface
UIM1-PWR 36 P4 PO
Power output for USIM1 card,
the voltage depends on the
USIM1 card type. Its output
current is up to 50mA.
1.8/3.0V voltage
domain, All lines of
USIM interface should
be protected against
ESD.
UIM1-DATA 34 P4 DIO
USIM1 Card data I/O, which has
been pulled up via a 10KR
resistor to USIM_VDD
internally. Do not pull it up or
down externally.
UIM1-CLK 32
P4 DO USIM1 clock output
UIM1-RESET 30
P4 DO USIM1 Reset output
SIM1_DET 66
P3 DI
USIM1 card detecting input
signal which has been pulled up
via a 10KR resistor to VDD_P3
internally.
UIM2_PWR 48 P4 PO
Power output for USIM2 card,
the voltage depends on the
USIM1 card type. Its output
current is up to 50mA.
1.8/3.0V voltage
domain, All lines of
USIM interface should
be protected against
ESD.
UIM2_DATA 42 P4 DIO
USIM2 Card data I/O, which has
been pulled up via a 10KR
resistor to USIM_VDD
internally. Do not pull it up or
down externally.
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