Hardware+Design V1.07

Smart Machine Smart Decision
Figure 35: EXT CODEC to MODULE timing
Figure 36: MODULE to EXT CODEC timing
Table 30: Timing parameters
Parameter Description Min Typ Max Unit
T(sync) PCM_SYNC cycle time – 125 – μs
T(synch) PCM_SYNC high time 400 500 – ns
T(syncl) PCM_SYNC low time – 124.5 – μs
T(clk) PCM_CLK cycle time – 488 – ns
T(clkh) PCM_CLK high time – 244 – ns
T(clkl) PCM_CLK low time – 244 – ns
T(susync)
PCM_SYNC setup time high before falling edge of
PCM_CLK
60 – – ns
T(hsync)
PCM_SYNC hold time after falling edge of
PCM_CLK
60 – – ns
T(sudin)
PCM_DIN setup time before falling edge of
PCM_CLK
50 – – ns
T(hdin)
PCM_DIN hold time after falling edge of
PCM_CLK
10 – – ns
T(pdout) Delay from PCM_CLK rising to PCM_DOUT valid – – 350 ns
SIM5320_Hardware Design_V1.07 2012-09-21
46