Specifications
2.3.2
ladex
2.3.1 Track 00
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INDEX
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..
200
"ue
TVP
I
1~4t------
1e~74
mMC
TYP
----~.~
.
The
drive
provides this interface signal once
I!very
revolution (16. 74 msec
typical)
to Indicate
the
beginning
of
the
track.
Normally
this
signal
is
a logical 1 (false)
and
makes
the transition
to
logical
0
(true)
for a period
of
approx-
imately
200
I1sec
once
each
revolution (see figure
2-8).
2.3.3 Ready
This
interface level, when true
Oogical
0). together
with
SEEK
COMPLETE, Indicates the drive
is
ready to read.
write,
or
seek, and that the signals are valid. When
this
Une
is
false
(Iogicall).
aU
seeking and
writing
is
inhibited
at
the
drive. .
READY
will
be
true after the drive is up
to·
speed
(±
2%)
for
two seconds. The typical time
for
READY
to become
true after power-on
is 12 seconds(21 seconds when the
low
power option has been utilized).
After
the automatic
aduator
recalibration process. typically
six
seconds.
SEEK
COMPLETE
wiD
also
become true. It is now
safe
to seek
the drive. but an additional two minutes should
be
allowed
for
thermal expansion to
stabUlze
before any
write
operations are perfonned.
FIGURE
2·8.
INDEX
TI.MING
This
interface
signal
Indicates a true state
(Ioglcal
0)
only when the read/write heads of the seleded
drive
are
at
track 00 (the outermost track)
and
the
access
circuitry
is
driving
current through phase one
of
the
stepper
motor.
This
signal
is
false (logical 1) when the
read/write
heads
of
the selected drive
are
not at track
00.
The
state of
this
line
is
undefined when
SEEK
COMPLETE
is
false.
The
active
state of
this
signal
(logical
0
level)
enables
WRITE
DATA
to
be
Written
onto the disk. The inactive state
of
the
signal
(logical
1
level)
enables data to
be
transferred
from
the
drive
and STEP pulses to reposition
the
head arm.
See figure 2-7
for
the
tlm1ng
sequences.
2.2.6 Reducecl Write
ClII1'eDt
and
Precom,...AtloD
The 706/712 provides for automatiC reduced
write
current switching. Optimum precompensation
15
12 nsec and
should
be
used on cyUnders
128
through 320.
2.3
CONTROL OUTPUT
UNES
')
2.2.5 Write Gate
The control output
signals
are driven
with
an open collector output stage capable of sinking a maximum
of
40 rnA
at
logical
0 (true),
with
a maximum voltage of 0.4 V measur.d
at
the driver. When the
line
driver
is
at
logical
1
(false).
the driver transitor is
off
and the collector cut-off current
is
a maximum of 250
~.
I
All
J5
output lines
are
enabled
by
their respective
DRIVE
SELECT .lines.
Agure 2-3 shows the recommended control signal driver/recetver
comblnation~
2·6