User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 87
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Bit Name Reset Access Description
5 CH5REQSTATUS 0 R Channel 5 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
4 CH4REQSTATUS 0 R Channel 4 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
3 CH3REQSTATUS 0 R Channel 3 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
2 CH2REQSTATUS 0 R Channel 2 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
1 CH1REQSTATUS 0 R Channel 1 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
0 CH0REQSTATUS 0 R Channel 0 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2
R
DMA transfers.
8.7.19 DMA_CHSREQSTATUS - Channel Single Request Status
Offset Bit Position
0xE18
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
Name
CH11SREQSTATUS
CH10SREQSTATUS
CH9SREQSTATUS
CH8SREQSTATUS
CH7SREQSTATUS
CH6SREQSTATUS
CH5SREQSTATUS
CH4SREQSTATUS
CH3SREQSTATUS
CH2SREQSTATUS
CH1SREQSTATUS
CH0SREQSTATUS
Bit Name Reset Access Description
31:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11 CH11SREQSTATUS 0 R Channel 11 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
10 CH10SREQSTATUS 0 R Channel 10 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
9 CH9SREQSTATUS 0 R Channel 9 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
8 CH8SREQSTATUS 0 R Channel 8 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
7 CH7SREQSTATUS 0 R Channel 7 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
6 CH6SREQSTATUS 0 R Channel 6 Single Request Status