User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 825
www.energymicro.com
List of Tables
2.1. Register Access Types ............................................................................................................................ 3
3.1. Energy Mode Description ......................................................................................................................... 8
3.2. EFM32GG Microcontroller Series ............................................................................................................... 8
4.1. Interrupt Request Lines (IRQ) .................................................................................................................. 13
5.1. Memory System Core Peripherals ............................................................................................................ 17
5.2. Memory System Low Energy Peripherals ................................................................................................... 18
5.3. Memory System Peripherals .................................................................................................................... 19
5.4. Device Information Table ........................................................................................................................ 23
7.1. MSC Flash Memory Mapping .................................................................................................................. 33
7.2. Lock Bits Page Structure ........................................................................................................................ 33
7.3. Revision Number Interpretation ................................................................................................................ 34
8.1. AHB bus transfer arbitration interval ......................................................................................................... 52
8.2. DMA channel priority ............................................................................................................................. 52
8.3. DMA cycle types ................................................................................................................................... 54
8.4. channel_cfg for a primary data structure, in memory scatter-gather mode ......................................................... 58
8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode ...................................................... 60
8.6. Address bit settings for the channel control data structure ............................................................................. 63
8.7. src_data_end_ptr bit assignments ............................................................................................................ 64
8.8. dst_data_end_ptr bit assignments ............................................................................................................ 65
8.9. channel_cfg bit assignments ................................................................................................................... 65
8.10. DMA cycle of six words using a word increment ........................................................................................ 68
8.11. DMA cycle of 12 bytes using a halfword increment .................................................................................... 69
8.12. User data assignments when DESCRECT is set ....................................................................................... 70
9.1. RMU Reset Cause Register Interpretation ................................................................................................ 100
10.1. EMU Energy Mode Overview ............................................................................................................... 109
10.2. EMU Entering a Low Energy Mode ....................................................................................................... 111
10.3. EMU Wakeup Triggers from Low Energy Modes ...................................................................................... 112
11.1. Configuration For Operating Frequencies ............................................................................................... 135
13.1. Reflex Producers ............................................................................................................................... 166
13.2. Reflex Consumers ............................................................................................................................. 167
14.1. EBI Intrapage hit condition for read on address Addr (non-mentioned Addr bits are unchanged) ......................... 181
14.2. EBI Enabling EBI_ADDR lines for transaction with address Addr and data Data ............................................. 184
14.3. EBI Mapping of AHB Transactions to External Device Transactions ............................................................. 187
14.4. EBI NAND Flash Register Select .......................................................................................................... 191
14.5. EBI NAND Flash Write Timing ............................................................................................................. 193
14.6. EBI NAND Flash Read Timing ............................................................................................................. 194
14.7. EBI NAND Flash Read/Write Timing Requirements .................................................................................. 194
14.8. EBI ECC Bit/Column Parity .................................................................................................................. 196
14.9. EBI ECC Byte/Row Parity ................................................................................................................... 196
14.10. EBI EBI_ECCPARITY valid bits .......................................................................................................... 197
14.11. EBI Error Detection Result ................................................................................................................. 197
15.1. Host Programming Operations ............................................................................................................. 257
15.2. ...................................................................................................................................................... 286
15.3. ...................................................................................................................................................... 330
15.4. ...................................................................................................................................................... 331
16.1. I
2
C Reserved I
2
C Addresses ................................................................................................................ 416
16.2. I
2
C Clock Modes ............................................................................................................................... 418
16.3. I
2
C Interactions in Prioritized Order ....................................................................................................... 421
16.4. I
2
C Master Transmitter ........................................................................................................................ 423
16.5. I
2
C Master Receiver ........................................................................................................................... 425
16.6. I
2
C STATE Values ............................................................................................................................. 426
16.7. I
2
C Transmission Status ...................................................................................................................... 426
16.8. I
2
C Slave Transmitter ......................................................................................................................... 429
16.9. I
2
C - Slave Receiver .......................................................................................................................... 430
16.10. I
2
C Bus Error Response .................................................................................................................... 431
17.1. USART Asynchronous vs. Synchronous Mode ........................................................................................ 448
17.2. USART Pin Usage ............................................................................................................................. 448
17.3. USART Data Bits ............................................................................................................................... 449
17.4. USART Stop Bits ............................................................................................................................... 449
17.5. USART Parity Bits ............................................................................................................................. 450
17.6. USART Oversampling ......................................................................................................................... 450
17.7. USART Baud Rates @ 4MHz Peripheral Clock ....................................................................................... 451
17.8. USART SPI Modes ............................................................................................................................ 463
17.9. USART I2S Modes ............................................................................................................................ 465
17.10. USART IrDA Pulse Widths ................................................................................................................. 470
18.1. UART Limitations ............................................................................................................................... 492
19.1. LEUART Parity Bit ............................................................................................................................. 495
19.2. LEUART Baud Rates ......................................................................................................................... 496
20.1. TIMER Counter Response in X2 Decoding Mode ..................................................................................... 525
20.2. TIMER Counter Response in X4 Decoding Mode ..................................................................................... 525
20.3. TIMER Events ................................................................................................................................... 536