User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 824
www.energymicro.com
27.1. VCMP Overview ................................................................................................................................ 673
27.2. VCMP 20 mV Hysteresis Enabled ......................................................................................................... 674
28.1. ADC Overview .................................................................................................................................. 682
28.2. ADC Conversion Timing ...................................................................................................................... 683
28.3. ADC Analog Power Consumption With Different WARMUPMODE Settings .................................................... 684
28.4. ADC RC Input Filter Configuration ........................................................................................................ 684
28.5. ADC Bias Programming ...................................................................................................................... 686
28.6. ADC Conversion Tailgating .................................................................................................................. 687
29.1. DAC Overview .................................................................................................................................. 705
29.2. DAC Bias Programming ...................................................................................................................... 707
29.3. DAC Sine Mode ................................................................................................................................ 708
30.1. OPAMP System Overview ................................................................................................................... 726
30.2. OPAMP Overview .............................................................................................................................. 727
30.3. Voltage Follower Unity Gain Overview ................................................................................................... 729
30.4. Inverting input PGA Overview .............................................................................................................. 729
30.5. Non-inverting PGA Overview ................................................................................................................ 730
30.6. Cascaded Inverting PGA Overview ....................................................................................................... 730
30.7. Cascaded Non-inverting PGA Overview ................................................................................................. 731
30.8. Two Op-amp Differential Amplifier Overview ........................................................................................... 732
30.9. Three Op-amp Differential Amplifier Overview ......................................................................................... 733
30.10. Dual Buffer ADC Driver Overview ....................................................................................................... 734
31.1. AES Key and Data Definitions .............................................................................................................. 736
31.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard ............................................ 736
31.3. AES Data and Key Register Operation .................................................................................................. 737
32.1. Pin Configuration ............................................................................................................................... 749
32.2. Tristated Output with Optional Pull-up or Pull-down .................................................................................. 750
32.3. Push-Pull Configuration ....................................................................................................................... 751
32.4. Open-drain ....................................................................................................................................... 751
32.5. EM4 Wake-up Logic ........................................................................................................................... 752
32.6. Pin n Interrupt Generation ................................................................................................................... 753
33.1. LCD Block Diagram ........................................................................................................................... 774
33.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ........................................ 776
33.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ............................................ 776
33.4. LCD Static Bias and Multiplexing - LCD_COM0 ....................................................................................... 776
33.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0 ................................................................................ 777
33.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1 ................................................................................ 777
33.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 ................................................................................. 777
33.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection ................................................................. 777
33.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 ................................................................ 778
33.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 778
33.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 .............................................................................. 778
33.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 .............................................................................. 778
33.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 ............................................................................... 779
33.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection ............................................................... 779
33.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 779
33.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 780
33.17. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 780
33.18. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 780
33.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 780
33.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 781
33.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 781
33.22. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 781
33.23. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 781
33.24. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 782
33.25. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 782
33.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 782
33.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 782
33.28. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 783
33.29. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 783
33.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 783
33.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 783
33.32. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 784
33.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 ........................................................................ 784
33.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 ........................................................................ 784
33.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2 ........................................................................ 784
33.36. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM3 ........................................................................ 785
33.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 ......................................................................... 785
33.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection ......................................................... 785
33.39. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM0 ........................................................ 785
33.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 ........................................................ 786
33.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2 ........................................................ 786
33.42. LCD 1/3 Bias and Quadruplex Multiplexing- LCD_SEG0-LCD_COM3 ......................................................... 786
33.43. LCD Clock System in LCD Driver ........................................................................................................ 792
33.44. LCD Block Diagram of the Animation Circuit ......................................................................................... 794