User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 822
www.energymicro.com
14.33. EBI TFT Size .................................................................................................................................. 199
14.34. EBI TFT Direct Drive from Internal Memory ........................................................................................... 200
14.35. EBI TFT Direct Drive from External Memory (non-multiplexed address/data) ................................................ 201
14.36. EBI TFT Direct Drive from External Memory (multiplexed address/data) ...................................................... 201
14.37. EBI Direct Drive Address ................................................................................................................... 202
14.38. EBI TFT Alpha Blending and Masking .................................................................................................. 203
14.39. EBI TFT Pixel Timing ........................................................................................................................ 206
14.40. EBI TFT Direct Drive Internal Timing ................................................................................................... 206
14.41. EBI TFT Direct Drive External Timing .................................................................................................. 206
14.42. EBI TFT Horizontal Porch Timing ........................................................................................................ 207
14.43. EBI TFT Vertical Porch Timing ........................................................................................................... 207
14.44. EBI TFT Pixel Timing: EBI_DCLK driven off Positive Edge Internal Clock .................................................... 207
14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock ................................................... 207
14.46. EBI TFT Interrupts ........................................................................................................................... 209
15.1. USB Block Diagram ........................................................................................................................... 241
15.2. Bus-powered Device .......................................................................................................................... 243
15.3. Self-powered Device .......................................................................................................................... 243
15.4. Self-powered Device (with bus-power switch) .......................................................................................... 244
15.5. OTG Dual Role Device (5V) ................................................................................................................ 245
15.6. OTG Dual Role Device (5V step-up regulator) ......................................................................................... 245
15.7. Host ................................................................................................................................................ 246
15.8. Transmit Transaction-Level Operation in Slave Mode ................................................................................ 253
15.9. Receive Transaction-Level Operation in Slave Mode ................................................................................ 253
15.10. Transmit FIFO Write Task in Slave Mode ............................................................................................. 258
15.11. Receive FIFO Read Task in Slave Mode .............................................................................................. 258
15.12. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode ....................................... 260
15.13. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode ........................................ 265
15.14. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode ................................................... 266
15.15. Normal Interrupt OUT/IN Transactions in Slave Mode ............................................................................. 270
15.16. Normal Interrupt OUT/IN Transactions in DMA Mode .............................................................................. 274
15.17. Normal Isochronous OUT/IN Transactions in Slave Mode ........................................................................ 278
15.18. Normal Isochronous OUT/IN Transactions in DMA Mode ......................................................................... 281
15.19. Processing a SETUP Packet .............................................................................................................. 289
15.20. Two-Stage Control Transfer ............................................................................................................... 292
15.21. Receive FIFO Packet Read in Slave Mode ........................................................................................... 293
15.22. Slave Mode Bulk OUT Transaction ...................................................................................................... 297
15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature ............................................................ 302
15.24. Isochronous OUT Core Internal Flow for Periodic Transfer Interrupt Feature ................................................ 303
15.25. Bulk IN Stall .................................................................................................................................... 307
15.26. USBTRDTIM Max Timing Case ERROR wrong image ............................................................................. 310
15.27. Slave Mode Bulk IN Transaction ......................................................................................................... 312
15.28. Slave Mode Bulk IN Transfer (Pipelined Transaction) .............................................................................. 314
15.29. Slave Mode Bulk IN Two-Endpoint Transfer .......................................................................................... 315
15.30. Periodic IN Application Flow for Periodic Transfer Interrupt Feature ............................................................ 319
15.31. Periodic IN Core Internal Flow for Periodic Transfer Interrupt Feature ......................................................... 321
15.32. SRP Detection by Core When Operating as A-device .............................................................................. 325
15.33. SRP Initiation by the Core When Acting as a B-Device ............................................................................ 326
15.34. HNP When the Core is an A-Device .................................................................................................... 327
15.35. HNP When the Core is a B-Device ..................................................................................................... 328
15.36. Core Interrupt Handler ...................................................................................................................... 336
16.1. I
2
C Overview .................................................................................................................................... 414
16.2. I
2
C-Bus Example ............................................................................................................................... 414
16.3. I
2
C START and STOP Conditions ......................................................................................................... 415
16.4. I
2
C Bit Transfer on I
2
C-Bus ................................................................................................................. 415
16.5. I
2
C Single Byte Write to Slave ............................................................................................................. 416
16.6. I
2
C Double Byte Read from Slave ......................................................................................................... 416
16.7. I
2
C Single Byte Write, then Repeated Start and Single Byte Read ............................................................... 416
16.8. I
2
C Master Transmitter/Slave Receiver with 10-bit Address ........................................................................ 417
16.9. I
2
C Master Receiver/Slave Transmitter with 10-bit Address ........................................................................ 417
16.10. I
2
C Master State Machine .................................................................................................................. 420
16.11. I
2
C Slave State Machine ................................................................................................................... 427
17.1. USART Overview ............................................................................................................................... 447
17.2. USART Asynchronous Frame Format .................................................................................................... 448
17.3. USART Transmit Buffer Operation ........................................................................................................ 452
17.4. USART Receive Buffer Operation ......................................................................................................... 454
17.5. USART Sampling of Start and Data Bits ................................................................................................ 455
17.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More ....................................................... 455
17.7. USART Local Loopback ...................................................................................................................... 456
17.8. USART Half Duplex Communication with External Driver ........................................................................... 457
17.9. USART Transmission of Large Frames .................................................................................................. 458
17.10. USART Transmission of Large Frames, MSBF ...................................................................................... 459
17.11. USART Reception of Large Frames ..................................................................................................... 459
17.12. USART ISO 7816 Data Frame Without Error ......................................................................................... 461
17.13. USART ISO 7816 Data Frame With Error ............................................................................................. 461