User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 82
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Bit Name Reset Access Description
31:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11 CH11ENC 0 W1 Channel 11 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
10 CH10ENC 0 W1 Channel 10 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
9 CH9ENC 0 W1 Channel 9 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
8 CH8ENC 0 W1 Channel 8 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
7 CH7ENC 0 W1 Channel 7 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
6 CH6ENC 0 W1 Channel 6 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
5 CH5ENC 0 W1 Channel 5 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
4 CH4ENC 0 W1 Channel 4 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
3 CH3ENC 0 W1 Channel 3 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
2 CH2ENC 0 W1 Channel 2 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
1 CH1ENC 0 W1 Channel 1 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
0 CH0ENC 0 W1 Channel 0 Enable Clear
Write to 1 to disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it completes
the DMA cycle, or it reads a channel_cfg memory location which has cycle_ctrl = b000, or an ERROR occurs on the AHB-Lite bus.
8.7.13 DMA_CHALTS - Channel Alternate Set Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
CH11ALTS
CH10ALTS
CH9ALTS
CH8ALTS
CH7ALTS
CH6ALTS
CH5ALTS
CH4ALTS
CH3ALTS
CH2ALTS
CH1ALTS
CH0ALTS
Bit Name Reset Access Description
31:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11 CH11ALTS 0 RW1 Channel 11 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
10 CH10ALTS 0 RW1 Channel 10 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
9 CH9ALTS 0 RW1 Channel 9 Alternate Structure Set