User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 74
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Bit Name Reset Access Description
5 CHPROT 0 W Channel Protection Control
Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access
is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged.
4:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 EN 0 W Enable DMA
Set this bit to enable the DMA controller.
8.7.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
CTRLBASE
Bit Name Reset Access Description
31:0 CTRLBASE 0x00000000 RW Channel Control Data Base Pointer
The base pointer for a location in system memory that holds the channel control data structure. This register must be written to point
to a location in system memory with the channel control data structure before the DMA can be used. Note that ctrl_base_ptr[8:0]
must be 0.
8.7.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer
Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000100
Access
R
Name
ALTCTRLBASE
Bit Name Reset Access Description
31:0 ALTCTRLBASE 0x00000100 R Channel Alternate Control Data Base Pointer