User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 73
www.energymicro.com
8.7 Register Description
8.7.1 DMA_STATUS - DMA Status Registers
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0B
0x0
0
Access
R
R
R
Name
CHNUM
STATE
EN
Bit Name Reset Access Description
31:21 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
20:16 CHNUM 0x0B R Channel Number
Number of available DMA channels minus one.
15:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:4 STATE 0x0 R Control Current State
State can be one of the following. Higher values (11-15) are undefined.
Value Mode Description
0 IDLE Idle
1 RDCHCTRLDATA Reading channel controller data
2 RDSRCENDPTR Reading source data end pointer
3 RDDSTENDPTR Reading destination data end pointer
4 RDSRCDATA Reading source data
5 WRDSTDATA Writing destination data
6 WAITREQCLR Waiting for DMA request to clear
7 WRCHCTRLDATA Writing channel controller data
8 STALLED Stalled
9 DONE Done
10 PERSCATTRANS Peripheral scatter-gather transition
3:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 EN 0 R DMA Enable Status
When this bit is 1, the DMA is enabled.
8.7.2 DMA_CONFIG - DMA Configuration Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W
W
Name
CHPROT
EN
Bit Name Reset Access Description
31:6 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)