User manual

...the world's most energy friendly microcontrollers

2012-04-24 - Giant Gecko Family - d0053_Rev0.96 72

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8.6 Register Map

The offset register address is relative to the registers base address.

Offset Name Type Description

0x000 DMA_STATUS R DMA Status Registers

0x004 DMA_CONFIG W DMA Configuration Register

0x008 DMA_CTRLBASE RW Channel Control Data Base Pointer Register

0x00C DMA_ALTCTRLBASE R Channel Alternate Control Data Base Pointer Register

0x010 DMA_CHWAITSTATUS R Channel Wait on Request Status Register

0x014 DMA_CHSWREQ W1 Channel Software Request Register

0x018 DMA_CHUSEBURSTS RW1 Channel Useburst Set Register

0x01C DMA_CHUSEBURSTC W1 Channel Useburst Clear Register

0x020 DMA_CHREQMASKS RW1 Channel Request Mask Set Register

0x024 DMA_CHREQMASKC W1 Channel Request Mask Clear Register

0x028 DMA_CHENS RW1 Channel Enable Set Register

0x02C DMA_CHENC W1 Channel Enable Clear Register

0x030 DMA_CHALTS RW1 Channel Alternate Set Register

0x034 DMA_CHALTC W1 Channel Alternate Clear Register

0x038 DMA_CHPRIS RW1 Channel Priority Set Register

0x03C DMA_CHPRIC W1 Channel Priority Clear Register

0x04C DMA_ERRORC RW Bus Error Clear Register

0xE10 DMA_CHREQSTATUS R Channel Request Status

0xE18 DMA_CHSREQSTATUS R Channel Single Request Status

0x1000 DMA_IF R Interrupt Flag Register

0x1004 DMA_IFS W1 Interrupt Flag Set Register

0x1008 DMA_IFC W1 Interrupt Flag Clear Register

0x100C DMA_IEN RW Interrupt Enable register

0x1010 DMA_CTRL RW DMA Control Register

0x1014 DMA_RDS RW DMA Retain Descriptor State

0x1020 DMA_LOOP0 RWH Channel 0 Loop Register

0x1024 DMA_LOOP1 RW Channel 1 Loop Register

0x1060 DMA_RECT0 RWH Channel 0 Rectangle Register

0x1100 DMA_CH0_CTRL RW Channel Control Register

... DMA_CHx_CTRL RW Channel Control Register

0x112C DMA_CH11_CTRL RW Channel Control Register