User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 718
www.energymicro.com
Bit Name Reset Access Description
Set this bit to halve the bias current.
13:12 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11:8 OPA2BIASPROG 0x7 RW Bias Programming Value for OPA2
These bits control the bias current level.
7 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6 HALFBIAS 1 RW Half Bias Current
Set this bit to halve the bias current.
5:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3:0 BIASPROG 0x7 RW Bias Programming Value
These bits control the bias current level.
29.5.14 DACn_OPACTRL - Operational Amplifier Control Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x0
0x0
0x0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
OPA2SHORT
OPA1SHORT
OPA0SHORT
OPA2LPFDIS
OPA1LPFDIS
OPA0LPFDIS
OPA2HCMDIS
OPA1HCMDIS
OPA0HCMDIS
OPA2EN
OPA1EN
OPA0EN
Bit Name Reset Access Description
31:25 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
24 OPA2SHORT 0 RW Short the non-inverting and Invering Input.
Set to short the non-inverting and invering input.
23 OPA1SHORT 0 RW Short the non-inverting and Invering Input.
Set to short the non-inverting and invering input.
22 OPA0SHORT 0 RW Short the non-inverting and Invering Input.
Set to short the non-inverting and Invering Input.
21:18 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17:16 OPA2LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative inputmux.
LPF DISABLE VALUE Description
PLPFDIS x1 Disables the low pass filter between positive pad and positive
input.
NLPFDIS 1x Disables the low pass filter between negative pad and
negative input.
15:14 OPA1LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative inputmux.
LPF DISABLE VALUE Description
PLPFDIS x1 Disables the low pass filter between positive pad and positive
input.
NLPFDIS 1x Disables the low pass filter between negative pad and
negative input.
13:12 OPA0LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative input mux.