User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 710
www.energymicro.com
29.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 DACn_CTRL RW Control Register
0x004 DACn_STATUS R Status Register
0x008 DACn_CH0CTRL RW Channel 0 Control Register
0x00C DACn_CH1CTRL RW Channel 1 Control Register
0x010 DACn_IEN RW Interrupt Enable Register
0x014 DACn_IF R Interrupt Flag Register
0x018 DACn_IFS W1 Interrupt Flag Set Register
0x01C DACn_IFC W1 Interrupt Flag Clear Register
0x020 DACn_CH0DATA RW Channel 0 Data Register
0x024 DACn_CH1DATA RW Channel 1 Data Register
0x028 DACn_COMBDATA W Combined Data Register
0x02C DACn_CAL RW Calibration Register
0x030 DACn_BIASPROG RW Bias Programming Register
0x054 DACn_OPACTRL RW Operational Amplifier Control Register
0x058 DACn_OPAOFFSET RW Operational Amplifier Offset Register
0x05C DACn_OPA0MUX RW Operational Amplifier Mux Configuration Register
0x060 DACn_OPA1MUX RW Operational Amplifier Mux Configuration Register
0x064 DACn_OPA2MUX RW Operational Amplifier Mux Configuration Register
29.5 Register Description
29.5.1 DACn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0
0
0x1
0x0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
REFRSEL
PRESC
REFSEL
CH0PRESCRST
OUTENPRS
OUTMODE
CONVMODE
SINEMODE
DIFF
Bit Name Reset Access Description
31:22 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
21:20 REFRSEL 0x0 RW Refresh Interval Select
Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in
DACn_CHxCTRL is set.
Value Mode Description
0 8CYCLES All channels with enabled refresh are refreshed every 8 prescaled cycles
1 16CYCLES All channels with enabled refresh are refreshed every 16 prescaled cycles
2 32CYCLES All channels with enabled refresh are refreshed every 32 prescaled cycles