User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 676
www.energymicro.com
27.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 VCMP_CTRL RW Control Register
0x004 VCMP_INPUTSEL RW Input Selection Register
0x008 VCMP_STATUS R Status Register
0x00C VCMP_IEN RW Interrupt Enable Register
0x010 VCMP_IF R Interrupt Flag Register
0x014 VCMP_IFS W1 Interrupt Flag Set Register
0x018 VCMP_IFC W1 Interrupt Flag Clear Register
27.5 Register Description
27.5.1 VCMP_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0x7
0
0
0x0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
HALFBIAS
BIASPROG
IFALL
IRISE
WARMTIME
HYSTEN
INACTVAL
EN
Bit Name Reset Access Description
31 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
30 HALFBIAS 1 RW Half Bias Current
Set this bit to 1 to halve the bias current. Table 27.1 (p. 673) .
29:28 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
27:24 BIASPROG 0x7 RW VCMP Bias Programming Value
These bits control the bias current level. Table 27.1 (p. 673) .
23:18 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17 IFALL 0 RW Falling Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
16 IRISE 0 RW Rising Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
15:11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10:8 WARMTIME 0x0 RW Warm-Up Time
Set warm-up time
Value Mode Description
0 4CYCLES 4 HFPERCLK cycles
1 8CYCLES 8 HFPERCLK cycles
2 16CYCLES 16 HFPERCLK cycles
3 32CYCLES 32 HFPERCLK cycles
4 64CYCLES 64 HFPERCLK cycles
5 128CYCLES 128 HFPERCLK cycles
6 256CYCLES 256 HFPERCLK cycles