User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 645
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Bit Name Reset Access Description
Value Mode Description
0 DISABLE CH2 output is disabled in idle phase
1 HIGH CH2 output is high in idle phase
2 LOW CH2 output is low in idle phase
3 DACCH0 CH2 output is connected to DAC CH0 output in idle phase
3:2 CH1 0x0 RW Channel 1 idlephase configuration
Value Mode Description
0 DISABLE CH1 output is disabled in idle phase
1 HIGH CH1 output is high in idle phase
2 LOW CH1 output is low in idle phase
3 DACCH0 CH1 output is connected to DAC CH0 output in idle phase
1:0 CH0 0x0 RW Channel 0 idlephase configuration
Value Mode Description
0 DISABLE CH0 output is disabled in idle phase
1 HIGH CH0 output is high in idle phase
2 LOW CH0 output is low in idle phase
3 DACCH0 CH0 output is connected to DAC CH0 output in idle phase
25.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration
(Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
AEX7
AEX6
AEX5
AEX4
AEX3
AEX2
AEX1
AEX0
IDLECONF7
IDLECONF6
IDLECONF5
IDLECONF4
IDLECONF3
IDLECONF2
IDLECONF1
IDLECONF0
Bit Name Reset Access Description
31:24 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
23 AEX7 0 RW ALTEX7 always excite enable
22 AEX6 0 RW ALTEX6 always excite enable
21 AEX5 0 RW ALTEX5 always excite enable
20 AEX4 0 RW ALTEX4 always excite enable
19 AEX3 0 RW ALTEX3 always excite enable
18 AEX2 0 RW ALTEX2 always excite enable